Datasheet

DRV8312
DRV8332
SLES256D –MAY 2010–REVISED JANUARY 2014 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range unless otherwise noted
(1)
VALUE
VDD to GND –0.3 V to 13.2 V
GVDD_X to GND –0.3 V to 13.2 V
PVDD_X to GND_X
(2)
–0.3 V to 70 V
OUT_X to GND_X
(2)
–0.3 V to 70 V
BST_X to GND_X
(2)
–0.3 V to 80 V
Transient peak output current (per pin), pulse width limited by internal over-current protection circuit. 16 A
Transient peak output current for latch shut down (per pin) 20 A
VREG to AGND –0.3 V to 4.2 V
GND_X to GND –0.3 V to 0.3 V
GND to AGND –0.3 V to 0.3 V
PWM_X, RESET_X to GND –0.3 V to 4.2 V
OC_ADJ, M1, M2, M3 to AGND –0.3 V to 4.2 V
FAULT, OTW to GND –0.3 V to 7 V
Maximum continuous sink current (FAULT, OTW) 9 mA
Maximum operating junction temperature range, T
J
-40°C to 150°C
Storage temperature, T
STG
–55°C to 150°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.
THERMAL INFORMATION
DRV8312 DRV8332
DDW DKD
THERMAL METRIC
(1)
UNITS
PACKAGE PACKAGE
44 PINS 36 PINS
13.3
θ
JA
Junction-to-ambient thermal resistance
(2)
24.5
(with heat sink)
θ
JCtop
Junction-to-case (top) thermal resistance
(3)
7.8 0.4
θ
JB
Junction-to-board thermal resistance
(4)
5.5 13.3
°C/W
ψ
JT
Junction-to-top characterization parameter
(5)
0.1 0.4
ψ
JB
Junction-to-board characterization parameter
(6)
5.4 13.3
θ
JCbot
Junction-to-case (bottom) thermal resistance
(7)
0.2 N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
2 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: DRV8312 DRV8332