Datasheet

DRV8312
DRV8332
SLES256D –MAY 2010–REVISED JANUARY 2014 www.ti.com
THEORY OF OPERATION
Special attention should be paid to the power-stage
POWER SUPPLIES
power supply; this includes component selection,
PCB placement, and routing. As indicated, each half-
To facilitate system design, the DRV8312/32 need
bridge has independent power-stage supply pin
only a 12-V supply in addition to H-Bridge power
(PVDD_X). For optimal electrical performance, EMI
supply (PVDD). An internal voltage regulator provides
compliance, and system reliability, it is important that
suitable voltage levels for the digital and low-voltage
each PVDD_X pin is decoupled with a ceramic
analog circuitry. Additionally, the high-side gate drive
capacitor (X5R or better) placed as close as possible
requiring a floating voltage supply, which is
to each supply pin. It is recommended to follow the
accommodated by built-in bootstrap circuitry requiring
PCB layout of the DRV8312/32 EVM board.
external bootstrap capacitor.
The 12-V supply should be from a low-noise, low-
To provide symmetrical electrical characteristics, the
output-impedance voltage regulator. Likewise, the 50-
PWM signal path, including gate drive and output
V power-stage supply is assumed to have low output
stage, is designed as identical, independent half-
impedance and low noise. The power-supply
bridges. For this reason, each half-bridge has a
sequence is not critical as facilitated by the internal
separate gate drive supply (GVDD_X), a bootstrap
power-on-reset circuit. Moreover, the DRV8312/32
pin (BST_X), and a power-stage supply pin
are fully protected against erroneous power-stage
(PVDD_X). Furthermore, an additional pin (VDD) is
turn-on due to parasitic gate charging. Thus, voltage-
provided as supply for all common circuits. Special
supply ramp rates (dv/dt) are non-critical within the
attention should be paid to place all decoupling
specified voltage range (see the Recommended
capacitors as close to their associated pins as
Operating Conditions section of this data sheet).
possible. In general, inductance between the power
supply pins and decoupling capacitors must be
avoided. Furthermore, decoupling capacitors need a SYSTEM POWER-UP/POWER-DOWN
short ground path back to the device. SEQUENCE
For a properly functioning bootstrap circuit, a small
Powering Up
ceramic capacitor (an X5R or better) must be
connected from each bootstrap pin (BST_X) to the The DRV8312/32 do not require a power-up
power-stage output pin (OUT_X). When the power- sequence. The outputs of the H-bridges remain in a
stage output is low, the bootstrap capacitor is high impedance state until the gate-drive supply
charged through an internal diode connected voltage GVDD_X and VDD voltage are above the
between the gate-drive power-supply pin (GVDD_X) undervoltage protection (UVP) voltage threshold (see
and the bootstrap pin. When the power-stage output the Electrical Characteristics section of this data
is high, the bootstrap capacitor potential is shifted sheet). Although not specifically required, holding
above the output potential and thus provides a RESET_A, RESET_B, and RESET_C in a low state
suitable voltage supply for the high-side gate driver. while powering up the device is recommended. This
In an application with PWM switching frequencies in allows an internal circuit to charge the external
the range from 10 kHz to 500 kHz, the use of 100-nF bootstrap capacitors by enabling a weak pulldown of
ceramic capacitors (X5R or better), size 0603 or the half-bridge output.
0805, is recommended for the bootstrap supply.
These 100-nF capacitors ensure sufficient energy Powering Down
storage, even during minimal PWM duty cycles, to
The DRV8312/32 do not require a power-down
keep the high-side power stage FET fully turned on
sequence. The device remains fully operational as
during the remaining part of the PWM cycle. In an
long as the gate-drive supply (GVDD_X) voltage and
application running at a switching frequency lower
VDD voltage are above the UVP voltage threshold
than 10 kHz, the bootstrap capacitor might need to be
(see the Electrical Characteristics section of this data
increased in value.
sheet). Although not specifically required, it is a good
practice to hold RESET_A, RESET_B and RESET_C
low during power down to prevent any unknown state
during this transition.
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