Datasheet
1
2
3
4
5
6
7
8
9
11
13
10
12
14
Thermal
Pad
(GND)
28
27
26
25
24
23
22
21
20
18
16
19
17
15
PWP Package
(Top View)
P0146-01
CP1
CP2
VCP
VM
COMPN
VM
OUT1
PGND1
PGND2
OUT2
OUT3
PGND3
COMPP
GND
GND
GND
IN1
EN1
IN2
EN2
IN3
EN3
NC
COMPO
FAULT
SLEEP
RESET
V3P3OUT
DRV8313
www.ti.com
SLVSBA5A –OCTOBER 2012–REVISED NOVEMBER 2012
PIN DESCRIPTIONS
PIN
TYPE DESCRIPTION EXTERNAL COMPONENTS OR CONNECTIONS
NAME NO.
Power and Ground
CP1 1 IO Charge-pump flying capacitor
Connect a 0.01-μF 100-V capacitor between CP1 and CP2.
CP2 2 IO Charge-pump flying capacitor
12, 20, 28,
GND – Device ground Connect to system ground
PPAD
Bypass to GND with a 0.47-μF 6.3-V ceramic capacitor. Use
V3P3OUT 15 O 3.3-V regulator output
for suppling external loads is permissible.
VCP 3 IO High-side gate drive voltage Connect a 0.1-μF 16-V ceramic capacitor to VM.
Connect to power supply (8.2 V–60 V). Connect both pins to
VM 4, 11 – Main power supply the same supply. Bypass to GND with a 10-µF (minimum)
capacitor.
Control
EN1 26 I Channel 1 enable Logic high enables OUT1. Internal pulldown
EN2 24 I Channel 2 enable Logic high enables OUT2. Internal pulldown
EN3 22 I Channel 3 enable Logic high enables OUT3. Internal pulldown
IN1 27 I Channel 1 input Logic input controls state of OUT1. Internal pulldown
IN2 25 I Channel 2 input Logic input controls state of OUT2. Internal pulldown
IN3 23 I Channel 3 input Logic input controls state of OUT3. Internal pulldown
Active-low reset input initializes internal logic and disables the
nRESET 16 I Reset input
outputs. Internal pulldown
Logic high to enable device, logic low to enter low-power sleep
nSLEEP 17 I Sleep-mode input
mode. Internal pulldown
Status
Logic low when in fault condition (overtemperature,
nFAULT 18 OD Fault
overcurrent, UVLO)
Comparator
COMPN 13 I Comparator negative input Negative input of comparator
COMPP 12 I Comparator positive input Positive input of comparator
nCOMPO 19 OD Comparator out Output of comparator. Open-drain output
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