Datasheet

DRV8302
SLES267 –AUGUST 2011 www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
PVDD = 8-60 V, T
C
= 25°C, unless specified under test condition
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C
V
GX_NORM
Gate driver Vgs voltage PVDD = 8–60V 9.5 11.5 V
I
oso1
Maximum source current setting 1, peak Vgs of FET equals to 2 V. REG 0x02 1.7 A
I
osi1
Maximum sink current setting 1, peak Vgs of FET equals to 8 V. REG 0x02 2.3 A
Gate output impedence during standby mode
R
gate_off
1.6 2.4 kΩ
when EN_GATE low (pins GH_x, GL_x)
SUPPLY CURRENTS
I
PVDD1_STB
PVDD1 supply current, standby EN_GATE is low. PVDD1 = 8V. 20 50 µA
EN_GATE is high, no load on gate drive
output, switching at 10 kHz,
I
PVDD1_OP
PVDD1 supply current, operating 15 mA
100 nC gate charge
I
PVDD1_HIZ
PVDD1 Supply current, HiZ EN_GATE is high, gate not switching 2 5 11 mA
INTERNAL REGULATOR VOLTAGE
A
VDD
AVDD voltage 6 6.5 7 V
D
VDD
DVDD voltage 3 3.3 3.6 V
VOLTAGE PROTECTION
V
PVDD_UV
Under voltage protection limit, PVDD 6 V
V
GVDD_UV
Under voltage protection limit, GVDD 8 V
V
GVDD_OV
Over voltage protection limit, GVDD 16 V
CURRENT PROTECTION, (VDS SENSING)
V
DS_OC
Drain-source voltage protection limit 0.125 2.4 V
T
oc
OC sensing response time 1.5 µs
OCTW pin reporting pulse stretch length for OC
T
OC_PULSE
64 µs
event
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