Datasheet

DRV8301
SLOS719B AUGUST 2011REVISED AUGUST 2013
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ELECTRICAL CHARACTERISTICS (continued)
PVDD = 6 V to 60 V, T
C
= 25°C, unless specified under test condition
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C
PVDD = 8V–60V, I
gate
= 30mA,
9.5 11.5
C
CP
= 22nF
V
GX_NORM
Gate driver Vgs voltage V
PVDD = 8V–60V, I
gate
= 30mA,
9.5 11.5
C
CP
= 220nF
PVDD = 6V–8V, I
gate
= 15mA,
8.8
C
CP
= 22nF
V
GX_MIN
Gate driver Vgs voltage V
PVDD = 6V–8V, I
gate
= 30mA,
8.3
C
CP
= 220nF
I
oso1
Maximum source current setting 1, peak Vgs of FET equals to 2 V. REG 0x02 1.7 A
I
osi1
Maximum sink current setting 1, peak Vgs of FET equals to 8 V. REG 0x02 2.3 A
I
oso2
Source current setting 2, peak Vgs of FET equals to 2 V. REG 0x02 0.7 A
I
osi2
Sink current setting 2, peak Vgs of FET equals to 8 V. REG 0x02 1 A
I
oso3
Source current setting 3, peak Vgs of FET equals to 2 V. REG 0x02 0.25 A
I
osi3
Sink current setting 3, peak Vgs of FET equals to 8 V. REG 0x02 0.5 A
Gate output impedence during standby mode
R
gate_off
1.6 2.4 kΩ
when EN_GATE low (pins GH_x, GL_x)
SUPPLY CURRENTS
I
PVDD1_STB
PVDD1 supply current, standby EN_GATE is low. PVDD1 = 8V. 20 50 µA
EN_GATE is high, no load on gate drive
output, switching at 10 kHz,
I
PVDD1_OP
PVDD1 supply current, operating 15 mA
100 nC gate charge
I
PVDD1_HIZ
PVDD1 Supply current, HiZ EN_GATE is high, gate not switching 2 5 10 mA
INTERNAL REGULATOR VOLTAGE
PVDD = 8V - 60V 6 6.5 7
A
VDD
AVDD voltage V
PVDD = 6V - 60V 5.5 6
D
VDD
DVDD voltage 3 3.3 3.6 V
VOLTAGE PROTECTION
PVDD falling 5.9
V
PVDD_UV
Under voltage protection limit, PVDD V
PVDD rising 6
V
GVDD_UV
Under voltage protection limit, GVDD GVDD falling 8 V
V
GVDD_OV
Over voltage protection limit, GVDD 16 V
CURRENT PROTECTION, (VDS SENSING)
PVDD = 8V - 60V 0.125 2.4
V
DS_OC
Drain-source voltage protection limit V
PVDD = 6V - 8V
(1)
0.125 1.491
T
oc
OC sensing response time 1.5 µs
OCTW pin reporting pulse stretch length for OC
T
OC_PULSE
64 µs
event
(1) Reduced A
VDD
voltage range results in limitations on settings for over current protection. See Table 9.
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