Datasheet

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DRV8301
www.ti.com SLOS719B –AUGUST 2011–REVISED AUGUST 2013
PCB LAYOUT RECOMMENDATIONS
Below are a few layout recommendations to utilize when designing a PCB for the DRV8301/2.
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1. The DRV8301/2 makes an electrical connection to GND through the PowerPAD. Always check to ensure that
the PowerPAD has been properly soldered (See PowerPAD application report, SLMA002).
2. C1/C2/C8/C9, PVDD decoupling capacitors should be placed close to their corresponding pins with a low
impedance path to device GND (PowerPAD).
3. C4, GVDD capacitor should be placed close its corresponding pin with a low impedance path to device GND
(PowerPAD).
4. C16/C17, AVDD & DVDD capacitors should be placed close to their corresponding pins with a low
impedance path to the AGND pin. It’s preferable to make this connection on the same layer.
5. AGND should be tied to device GND (PowerPAD) through a low impedance trace/copper fill.
6. Add stitching vias to reduce the impedance of the GND path from the top to bottom side.
7. Try to clear the space around and underneath the DRV8301/2 to allow for better heat spreading from the
PowerPAD.
Table 10. Recommended Values
DESIGNATOR PIN RECOMMENDED VALUE DESCRIPTION
C1 PVDD1 – pin 29 2.2uF CAP CER 2.2UF 100V 10% X7R
C2 PVDD1 – pin 29 0.1uF CAP CER 0.1UF 100V 10% X7R
C8 PVDD2 – pins 53 & 54 2.2uF CAP CER 2.2UF 100V 10% X7R
C9 PVDD2 – pins 53 & 54 0.1uF CAP CER 0.1UF 100V 10% X7R
C4 GVDD – pin 13 2.2uF CAP CER 2.2UF 25V 10% X7R
C16 AVDD – pin 27 1.0uF CAP CER 1UF 25V 10% X7R
C17 DVDD – pin 23 1.0uF CAP CER 1UF 25V 10% X7R
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Product Folder Links: DRV8301