Datasheet
DRV8301
www.ti.com
SLOS719B –AUGUST 2011–REVISED AUGUST 2013
Therefore, each SPI Control / Response pair requires two full 16-bit shift cycles to complete.
Table 2. SPI Input Data Control Word Format
R/W Address Data
Word Bit B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Command W0 A3 A2 A1 A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Table 3. SPI Output Data Response Word Format
R/W Data
Word Bit B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Command F0 A3 A2 A1 A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SPI Control and Status Registers
Read / Write Bit
The MSB bit of SDI word (W0) is read/write bit. When W0 = 0, input data is a write command; when W0 = 1,
input data is a read command, and the register value will send out on the same word cycle from SDO from D10
to D0.
Address Bits
Table 4. Register Address
Register
Register Type Address [A3..A0] Description Read and Write Access
Name
Status Report occurred faults after previous
0 0 0 0 R (auto reset to default values after read)
Register 1 reading
Status
Device ID: R
Register
Status Device ID and report occurred faults
0 0 0 1
Fault report: R (auto reset to default
Register 2 after previous reading
values after read)
Control
0 0 1 0 R/W
Register 1
Control
Register
Control
0 0 1 1 R/W
Register 2
SPI Data Bits
Status Registers
Table 5. Status Register 1 (Address: 0x00) (all default values are zero)
Register
Address D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Name
Status
0x00 FAULT GVDD_UV PVDD_UV OTSD OTW FETHA_OC FETLA_OC FETHB_OC FETLB_OC FETHC_OC FETLC_OC
Register 1
Table 6. Status Register 2 (Address: 0x01) (all default values are zero)
Address Register Name D7 D6 D5 D4 D3 D2 D1 D0
0x01 Status GVDD_OV Device ID
Register 2
0 0 0 0
• All status register bits are in latched mode. Read each status register will reset the bits in this register. Read
fault register twice to get an updated status condition.
• EN_GATE toggling with “low” level holding longer than 10µS will force a shut down and start up sequence
and reset all values in status registers including GVDD_OV fault.
• EN_GATE toggling (quick fault reset) with low level holding less than 10uS or GATE_RESET high (in SPI) will
reset all values in status registers except GVDD_OV fault which will still be latched as a fault.
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