Datasheet

SupplyRamp
Supply
Enable
Timeforac-coupling
capacitorstocharge
R11
R12
R13
Cy
VSUP_MO
UVP pin11
DRV603
SLOS617C –JANUARY 2009–REVISED NOVEMBER 2009 www.ti.com
POP-FREE POWER UP
Pop-free power up is ensured by keeping the SD (shutdown pin) low during power-supply ramp up and ramp
down. The SD pin should be kept low until the input ac-coupling capacitors are fully charged before asserting the
SD pin high to achieve pop-less power up. Figure 14 illustrates the preferred sequence.
Figure 14. Power-Up Sequence
EXTERNAL UNDERVOLTAGE DETECTION
External undervoltage detection can be used to
mute/shut down the DRV603 before an input device
can generate a pop.
The shutdown threshold at the UVP pin is 1.25 V.
The user selects a resistor divider to obtain the
shutdown threshold and hysteresis for the specific
application. The thresholds can be determined as
follows:
V
UVP
= 1.25 V × (R11 + R12) / R12
Hysteresis = 5 μA × R13 × (R11 + R12) / R12
with the condition R13 >> R11//R12.
For example, to obtain V
UVP
= 5 V and 1-V
hysteresis, R11 = 3 kΩ, R12 = 1 kΩ and R13 = 50
kΩ.
CAPACITIVE LOAD
The DRV603 has the ability to drive a high capacitive load up to 220 pF directly. Higher capacitive loads can be
accepted by adding a series resistor of 47 Ω or larger.
LAYOUT RECOMMENDATIONS
A proposed layout for the DRV603 can be seen in the DRV603EVM User's Guide (SLOU248), and the Gerber
files can be downloaded from http://focus.ti.com/docs/toolsw/folders/print/drv603evm.html. To access this
information, open the DRV603 product folder and look in the Tools and Software folder.
GAIN-SETTING RESISTORS
The gain-setting resistors, R
IN
and R
fb
, must be placed close to the input pins to minimize capacitive loading on
these input pins and to ensure maximum stability of the DRV603. For the recommended PCB layout, see the
DRV603EVM user's guide (SLOU248).
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Product Folder Link(s): DRV603