Datasheet
SCL
SDA
th2 t(buf)
tsu2 tsu3
StartCondition
StopCondition
SCL
SDA
t
w(H)
t
w(L)
t
su1
t
h1
DRV2667
www.ti.com
SLOS751A –MARCH 2013–REVISED JANUARY 2014
TIMING CHARACTERISTICS
For I
2
C interface signals over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
SCL
Frequency, SCL No wait states 400 kHz
t
W(H)
Pulse duration, SCL high 0.6 μs
t
W(L)
Pulse duration, SCL low 1.3 μs
t
SU1
Setup time, SDA to SCL 100 ns
t
H1
Hold time, SCL to SDA 10 ns
t
(BUF)
Bus free time between stop and start condition 1.3 μs
t
SU2
Setup time, SCL to start condition 0.6 μs
t
H2
Hold time, start condition to SCL 0.6 μs
t
SU3
Setup time, SCL to stop condition 0.6 μs
Figure 1. SCL and SDA Timing
Figure 2. Start and Stop Conditions Timing
Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: DRV2667