Datasheet

Page 0
0x00
0xFF
Page 1
Page 2
Page 7
Page 8
0x000
0x0FF
0x100
0x1FF
0x600
0x6FF
0x700
0x7FF
Control Registers
RAM
DRV2667
www.ti.com SLOS751A –MARCH 2013–REVISED JANUARY 2014
MEMORY INTERFACE
To maintain compatibility with the majority of standard I
2
C controllers, the DRV2667 uses 8-bit addressing. In
order to access 2 kB of RAM, a paging system is employed. The page register is located at address 0xFF. There
are 8 memory pages that make up the 2048 bytes with 256 bytes on each page. Note that page 0 is reserved for
register control space as defined in the previous section.
Since the device addresses are only 8-bits, a special exception exists to distinguish whether the user is trying to
write the page register at address 0xFF or the memory location at 0xPFF, where P represents the page number
as shown in Figure 27. In order to access the page register, the programmer must use a Single-Byte I
2
C protocol
(see General I2C Operation section) to perform a single-byte write to memory location 0xFF. To access the
memory location in RAM at register 0xFF, the user must use the Incremental Multiple-Byte protocol, and the
beginning address must be less than 0xFF.
As a convenience for filling memory across multiple pages, the page register will automatically increment for
multiple-byte writes that cross the page boundaries. Multiple-byte reads across page boundaries are not
supported. All memory is retained in the device until the device power is cycled.
Figure 27. Memory Map
Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: DRV2667