Datasheet

DRV2667

www.ti.com

SLOS751A –MARCH 2013–REVISED JANUARY 2014

Control 2 (Address: 0x02)

Bit 7 6 5 4 3 2 1 0

Function DEV_RST STANDBY Timeout[1] Timeout[0] EN_Override GO

Type Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write

Default 0 1 0 0 0 0

DEV_RST Device Reset. When the DEV_RST bit is set, the device will immediately stop any transaction

in process, reset all of its internal registers to their default values as well as put itself in

STANDBY mode.

STANDBY Low-Power Standby

0: Device is active and ready to receive a signal

1: Device is in low-power standby mode

Timeout[1:0] Time period between when the FIFO runs empty and the DRV2667 goes into idle mode,

powering down the boost converter and amplifier.

0: 5 ms

1: 10 ms

2: 15 ms

3: 20 ms

EN_Override Override bit for the boost converter and amplifier enables

0: Boost converter and amplifier enables are controlled by DRV2667 logic

1: Boost converter and amplifier are enabled indefinitely

GO Starts the playback of DRV2667 internal waveform memory as indicated by Sequence

registers 0x03 through 0x0A. This bit remains high during the execution of waveform

playback, and self-clears upon completion of playback. The user may optionally clear this bit

to cancel waveform playback.

Waveform Sequencer (Address: 0x03 to Address 0x0A)

Bit 7 6 5 4 3 2 1 0

Function Wavform[7] Wavform[6] Wavform[5] Wavform[4] Wavform[3] Wavform[2] Wavform[1] Wavform[0]

Type Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write

Default 0 0 0 0 0 0 0 0

Wavform[7:0] When the Go bit is asserted, the waveform processing engine will go to register address 0x03

and play the waveform ID that is indicated there. After completion of that waveform, the engine

proceeds to register address 0x04 to play that waveform ID. If the ID value is zero, the playback

process terminates. Otherwise this process repeats until it finds a waveform ID of zero, or all 8

waveforms are played.

Product Folder Links: DRV2667