Datasheet

A6 A0 ACK
Acknowledge
I CDevice Addressand
Read/WriteBit
2
R/WA6 A0 R/W ACK A0 ACK D7 D0 ACK
Start
Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
LastDataByte
ACK
FirstDataByte
RepeatStart
Condition
Not
Acknowledge
I CDevice Addressand
Read/WriteBit
2
Subaddress OtherDataBytes
A7 A6 A5 D7 D0 ACK
Acknowledge
D7 D0
T0484-01
A6 A5 A0 R/W ACK A7 A6 A5 A4 A0 ACK A6 A5 A0 ACK
Start
Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
I CDevice Addressand
Read/WriteBit
2
Subaddress DataByte
D7 D6 D1 D0 ACK
I CDevice Addressand
Read/WriteBit
2
Not
Acknowledge
R/WA1 A1
RepeatStart
Condition
T0483-01
DRV2667
www.ti.com SLOS751A –MARCH 2013–REVISED JANUARY 2014
SINGLE-BYTE READ
As shown in Figure 25, a single-byte data-read transfer begins with the master device transmitting a start
condition followed by the I
2
C device address and the read/write bit. For the data-read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte of the internal memory
address to be read. As a result, the read/write bit is set to a 0.
After receiving the DRV2667 address and the read/write bit, the device responds with an acknowledge bit. The
master then sends the internal memory address byte, after which the device issues an acknowledge bit. The
master device transmits another start condition followed by the device address and the read/write bit again. This
time, the read/write bit is set to 1, indicating a read transfer. Next, the device transmits the data byte from the
memory address being read. After receiving the data byte, the master device transmits a not-acknowledge
followed by a stop condition to complete the single-byte data read transfer.
The device address is 0x59 (7-bit), or 1011001 in binary.
Figure 25. Single-Byte Read Transfer
MULTIPLE-BYTE READ
A multiple-byte data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes
are transmitted by the DRV2667 to the master device as shown in Figure 26. With the exception of the last data
byte, the master device responds with an acknowledge bit after receiving each data byte.
Figure 26. Multiple-Byte Read Transfer
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