Datasheet

7-BitSlave Address
R/
W
8-BitRegister Address(N)
A
8-BitRegisterDataFor
Address(N)
Start Stop
SDA
SCL
7
6
5
4
3
2 1
0
7
6
5
4
3
2 1
0
7
6
5
4
3
2 1
0
7
6
5
4
3
2 1
0
A
8-BitRegisterDataFor
Address(N)
A A
T0035-01
DRV2667
www.ti.com SLOS751A –MARCH 2013–REVISED JANUARY 2014
GENERAL I
2
C OPERATION
The I
2
C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. The bus transfers data serially, one bit at a time. The 8-bit address and data bytes are transferred most-
significant bit (MSB) first. In addition, each byte transferred on the bus is acknowledged by the receiving device
with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the
bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data
terminal (SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition on
SDA indicates a start, and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within
the low time of the clock period. Figure 22 shows a typical sequence. The master generates the 7-bit slave
address and the read/write (R/W) bit to open communication with a slave device and then waits for an
acknowledge condition. The slave device holds SDA low during the acknowledge clock period to indicate
acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device is
addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals
via a bidirectional bus using a wired-AND connection.
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is
shown in Figure 22.
Use external pull up resistors for the SDA and SCL signals to set the logic-high level for the bus. Pull up resistors
between 660 Ω and 4.7 kΩ are recommended. Do not allow the SDA and SCL voltages to exceed the device
supply voltage, VDD.
Figure 22. Typical I
2
C Sequence
The DRV2667 operates as an I
2
C slave with 1.8 V logic thresholds, but can operate up to the VDD voltage. The
device address is 0x59 (7-bit), or 1011001 in binary. This is equivalent to 0xB2 (8-bit) for writing and 0xB3 (8-bit)
for reading.
SINGLE-BYTE AND MULTIPLE-BYTE TRANSFERS
The serial control interface supports both single-byte and multiple-byte read/write operations for all registers.
During multiple-byte read operations, the device responds with data, a byte at a time, starting at the register
assigned, as long as the master device continues to respond with acknowledges.
The device supports sequential I
2
C addressing. For write transactions, if a register is issued followed by data for
that register and all the remaining registers that follow, a sequential I
2
C write transaction has taken place. For I
2
C
sequential write transactions, the register issued then serves as the starting point, and the amount of data
subsequently transmitted, before a stop or start is transmitted, determines to how many registers are written.
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