Datasheet
DRV11873
SLWS237 –NOVEMBER 2012
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
MIN MAX
VCC -0.3 20
CS -0.3 3.6
Input voltage range PWMIN, FS, FR -0.3 6 V
GND -0.3 0.3
COM -1 20
U, V, W -1 20
FG, RD -0.3 20
VCP -0.3 25
Output voltage range V
CPN -0.3 20
CPP -0.3 25
V5 -0.3 6
Human body model, HBM 4
kV
Electrostatic discharge (ESD) Charge device model, CBM 1
Machine model, MM 200 V
T
J
Operating junction temperature -40 125 °C
T
stg
Storage temperature -55 150 °C
THERMAL INFORMATION
DRV11873
THERMAL METRIC
(1)
PWP UNITS
16 PINS
θ
JA
Junction-to-ambient thermal resistance
(2)
39.4
θ
JCtop
Junction-to-case (top) thermal resistance
(3)
30.3
θ
JB
Junction-to-board thermal resistance
(4)
25.6
°C/W
ψ
JT
Junction-to-top characterization parameter
(5)
0.5
ψ
JB
Junction-to-board characterization parameter
(6)
10.2
θ
JCbot
Junction-to-case (bottom) thermal resistance
(7)
3.6
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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