Datasheet

PEAK PEAK
SENSE PEAK
1 900mA
I 66.67k ;66.67k R 2M
R R
W
= × × W W < < W
5
KEEP KEEP
s
t s C F 10
F
é ù
= ×
é ù é ù
ë û ë û
ê ú
ë û
I
PEAK
I
HOLD
t
KEEP
t
I
SOLENOID
EN
t
DRV110
www.ti.com SLVSBA8A –MARCH 2012–REVISED JANUARY 2013
FUNCTIONAL DESCRIPTION
DRV110 controls the current through the solenoid as shown in Figure 3. Activation starts when EN pin voltage is
pulled high either by an external driver or internal pull-up. In the beginning of activation, DRV110 allows the load
current to ramp up to the peak value I
PEAK
and it regulates it at the peak value for the time, t
KEEP
, before reducing
it to I
HOLD
. The load current is regulated at the hold value as long as the EN pin is kept high. The initial current
ramp-up time depends on the inductance and resistance of the solenoid. Once EN pin is driven to GND, DRV110
allows the solenoid current to decay to zero.
Figure 3. Typical Current Waveform Through the Solenoid
t
KEEP
is set externally by connecting a capacitor to the KEEP pin. A constant current is sourced from the KEEP
pin that is driven into an external capacitor resulting in a linear voltage ramp. When the KEEP pin voltage
reaches 100 mV, the current regulation reference voltage, V
REF
, is switched from V
PEAK
to V
HOLD
. Dependency of
t
KEEP
from the external capacitor size can be calculated by:
(1)
The current control loop regulates, cycle-by-cycle, the solenoid current by sensing voltage at the SENSE pin and
controlling the external switching device gate through the OUT pin. During the ON-cycle, the OUT pin voltage is
driven and kept high (equal to VIN voltage) as long as the voltage at the SENSE pin is less than V
REF
allowing
current to flow through the external switch. As soon as the voltage at the SENSE pin is above V
REF
, the OUT pin
voltage is immediately driven and kept low until the next ON-cycle is triggered by the internal PWM clock signal.
In the beginning of each ON-cycle, the OUT pin voltage is driven and kept high for at least the time determined
by the minimum PWM signal duty cycle, D
MIN
.
V
PEAK
and V
HOLD
depend on fixed resistance values R
PEAK
and R
HOLD
as shown in Figure 4. If the PEAK pin is
connected to ground, the peak current reference voltage, V
PEAK
, is at it’s default value (internal setting). The
V
PEAK
value can alternatively be set by connecting an external resistor to ground from the PEAK pin. For
example, if a 50-kΩ (= R
PEAK
) resistor is connected between PEAK and GND, and R
SENSE
= 1 Ω, then the
externally set I
PEAK
level will be 900 mA. If R
PEAK
= 200 kΩ and R
SENSE
= 1 Ω, then the externally set I
PEAK
level
will be 300 mA. In case R
SENSE
= 2 Ω instead of 1 Ω, then I
PEAK
= 450 mA (when R
PEAK
= 50 kΩ) and
I
PEAK
= 150 mA (when R
PEAK
= 200 kΩ). External setting of the HOLD current, I
HOLD
, works in the same way, but
the current levels are 1/6 of the I
PEAK
levels. External settings for I
PEAK
and I
HOLD
are independent of each other.
If R
PEAK
is decreased below 33.33 kΩ (typ value), then the reference is clamped to the internal setting. The same
is valid for R
HOLD
and I
HOLD
. I
PEAK
and I
HOLD
values can be calculated by using the formula below.
(2)
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