Datasheet
DRV110
SLVSBA8A –MARCH 2012–REVISED JANUARY 2013
www.ti.com
ELECTRICAL CHARACTERISTICS
V
IN
= 14 V, T
A
= -40°C to 105°C, over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
Standby current EN = 0, V
IN
= 14 V, bypass deactivated 200 250
µA
Quiescent current EN = 1, V
IN
= 14 V, bypass deactivated 360 570
I
Q
EN = 0, I
VIN
= 2 mA, bypass activated 10.5 15 19
Internally regulated supply V
EN = 1, I
VIN
= 2 mA, bypass activated 14.5 15 15.5
GATE DRIVER
V
DRV
Gate drive voltage Supply voltage in regulation (I
VIN
> 1 mA) V
IN
V
I
DRV_SINK
Gate drive sink current V
OUT
= 15 V; V
IN
= 15 V 8 15 mA
I
DRV_SOURCE
Gate drive source current V
OUT
= GND; V
IN
= 15 V -15 -10 mA
f
PWM
PWM clock frequency OSC = GND 15 20 27 kHz
D
MAX
Maximum PWM duty cycle 100 %
D
MIN
Minimum PWM duty cycle 7.5 %
Delay between EN going high until gate driver
t
D
Start-up delay 50 µs
starts switching, f
PWM
= 20 kHz
CURRENT CONTROLLER, INTERNAL SETTINGS
I
PEAK
Peak current R
SENSE
= 1 Ω, PEAK = GND 270 300 330 mA
I
HOLD
Hold current R
SENSE
= 1 Ω, HOLD = GND 40 50 65 mA
CURRENT CONTROLLER, EXTERNAL SETTINGS
Externally set keep time at peak
t
KEEP
C
KEEP
= 1 µF 100 ms
current
R
PEAK
= 50 kΩ 900
V
PEAK
Externally set V
PEAK
mV
R
PEAK
= 200 kΩ 300
R
HOLD
= 50 kΩ 150
V
HOLD
Externally set V
HOLD
mV
R
HOLD
= 200 kΩ 50
R
OSC
= 50 kΩ 60
f
PWM
Externally set PWM clock frequency kHz
R
OSC
= 200 kΩ 20
LOGIC INPUT LEVELS (EN)
V
IL
Input low level 1.3 V
V
IH
Input high level 1.65 V
R
EN
Input pull-up resistance 350 500 kΩ
LOGIC OUTPUT LEVELS (STATUS)
V
OL
Output low level Pull-down activated, I
STATUS
= 2 mA 0.3 V
I
IL
Output leakage current Pull-down deactivated, V(STATUS) = 5 V 2 µA
UNDERVOLTAGE LOCKOUT
V
UVLO
Undervoltage lockout threshold 4.6 V
THERMAL SHUTDOWN
Junction temperature startup
T
TSU
140 °C
threshold
Junction temperature shutdown
T
TSD
160 °C
threshold
6 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: DRV110