Datasheet
DRV110
www.ti.com
SLVSBA8A –MARCH 2012–REVISED JANUARY 2013
ABSOLUTE MAXIMUM RATINGS
(1)(2)
VALUE UNIT
VIN Input voltage range –0.3 to 20 V
Voltage range on EN, STATUS, PEAK, HOLD, OSC, SENSE, KEEP –0.3 to 7 V
Voltage range on OUT –0.3 to 20 V
HBM (human body model) 2000
ESD rating V
CDM (charged device model) 500
T
J
Operating virtual junction temperature range –40 to 125 °C
T
stg
Storage temperature range –65 to 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
I
Q
Supply current 1 1.5 3 mA
V
IN
Device will start sinking current when V
IN
> 15 V to limit V
IN
6 15 V
C
IN
Input capacitor between VIN and GND
(1)
1 4.7 µF
L Solenoid inductance 1 H
T
A
Operating ambient temperature -40 105 °C
(1) 4.7-µF input capacitor and full wave rectified 230-Vrms AC supply results in approximately 500-mV supply ripple.
THERMAL INFORMATION
DRV110
THERMAL METRIC PWP UNITS
8 PINS 14 PINS
θ
JA
Junction-to-ambient thermal resistance
(1)
183.8 122.6
θ
JCtop
Junction-to-case (top) thermal resistance
(2)
69.2 51.2
θ
JB
Junction-to-board thermal resistance
(3)
112.6 64.3
°C/W
ψ
JT
Junction-to-top characterization parameter
(4)
10.4 6.5
ψ
JB
Junction-to-board characterization parameter
(5)
110.9 63.7
θ
JCbot
Junction-to-case (bottom) thermal resistance
(6)
N/A N/A
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(4) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(5) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: DRV110