Datasheet

DRV104
2
SBVS036B
www.ti.com
Supply Voltage V
S
, V
PS1
, V
PS2
(2)
....................................................... +40V
Input Voltage, Master, SYNC ......................................... –0.2V to +5.5V
(3)
PWM Adjust Input .......................................................... –0.2V to +5.5V
(3)
Delay Adjust Input .......................................................... –0.2V to +5.5V
(3)
Frequency Adjust Input .................................................. –0.2V to +5.5V
(3)
Status OK Flag and OUT .................................................... –0.2V to V
S
(4)
Boot Voltage ............................................................................... V
S
+ 10V
Operating Temperature Range ...................................... –55°C to +125°C
Storage Temperature ..................................................... –65°C to +150°C
Junction Temperature .................................................................... +150°C
NOTES: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may de-
grade device reliability. (2) See the Bypass section for discussion about
operating near the maximum supply. (3) Higher voltage may be applied if
current is limited to 2mA. (4) Status OK flag will internally current limit at
about 10mA.
ABSOLUTE MAXIMUM RATINGS
(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
SPECIFIED
PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY
DRV104 PowerPAD HTSSOP-14 PWP –40°C to +85°C DRV104 DRV104PWP Rails, 90
" """"DRV104PWPR Tape and Reel, 2000
PACKAGE/ORDERING INFORMATION
(1)
LOGIC BLOCK DIAGRAM
Delay
Adj
Input
On
Off
Thermal Shutdown
Over Current
Status OK
Flag
+V
S
Coil
OUT2
C
BOOT
Oscillator
1.25V V
REF
PWM
Osc Freq
Adj
Duty Cycle
Adj
GND
Delay
DRV104
OUT1
+V
PS
1
+V
PS
2
C
D
R
PWM
DMOS
DMOS
2.75 • I
REF
R
FREQ
I
REF
13 10
11 513
14
SYNC
12
Master
4
2
8
9
6
7
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this document, or see the TI web site
at www.ti.com.