Datasheet

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DP83856
6.0 Electrical Specifications (Continued)
6.5 RGMII Timing
6.5.1 Transmit and Receive Multiplexing and Timing
TX [3:0]
T
skewT
TXEN_ER
TCK
TXD[3:0] TXD[7:4]
TX_EN
TX_ER
TXD[3:0]
TXD[7:4]
TX_EN TX_ER
T
cyc
Parameter Description Notes Min Typ Max Units
T
skewT
TX to Clock skew (at receiver, PHY), HP mode Note 1 1.0 2.0 ns
T
skewT
TX to Clock skew (at receiver, PHY), 3COM mode Note 4 -900 900 ps
T
skewR
RX to Clock skew (at transmitter, PHY), HP mode Note 4 -500 500 ps
T
setupR
RX to Clock setup (at transmitter, PHY), 3COM mode Note 4 1.4 ns
T
holdR
RX to Clock hold (at transmitter, PHY), 3COM mode Note 4 1.2 ns
T
cyc
Clock Period Note 2, 4 7.2 8 8.8 ns
T
Duty_G
Duty Cycle for gigabit Note 3 45 50 55 %
T
Duty_T
Duty Cycle for 10/100 BASE-T Note 3 40 50 60 %
T
r
/T
f
Rise/Fall Time (20 -80%) Note 4 1.0 ns
Note 1: The PC board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns is added to the associated clock signal.
Note 2: For 10 Mbps and 100 Mbps, Tcyc will scale to 400ns +-40ns and 40ns +-4ns.
Note 3: Duty cycle may be stretched or shrunk during speed changes or while transitioning to a received packet’s clock domain as long as minimum duty
cycle is not violated and stretching occurs for no more that three Tcyc of the lowest speed transitioned between.
Note 4: Guaranteed by design. Not tested.
RCK
RX [3:0]
RXDV_ER
T
skewR
T
setupR
RXD[3:0] RXD[7:4]
RX_DV
RX_ER
RXD[3:0]
RXD[7:4]
RX_DV
RX_ER
T
cyc
T
holdR