Datasheet

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DP83865
1.0 Pin Description (Continued)
TXD0/TX0
TXD1/TX1
TXD2/TX2
TXD3/TX3
TXD4
TXD5
TXD6
TXD7
I76
75
72
71
68
67
66
65
TRANSMIT DATA: These signals carry 4B data nibbles (TXD[3:0]) during 10
Mbps and 100 Mbps MII mode, 4-bit data (TX[3:0]) in RGMII mode, and 8-bit
data (TXD[7:0]) in 1000 Mbps GMII mode. They are synchronous to the trans-
mit clocks (TX_CLK, TCK, GTX_CLK).
Transmit data is input to PHY. In MII or GMII mode, the transmit data is en-
abled by TX_EN. In RGMII mode, the transmit data is enabled by TXEN_ER.
TX_EN/TXEN_ER I 62 TRANSMIT ENABLE or TRANSMIT ENABLE/ERROR: In MII or GMII mode,
it is an active high input sourced from MAC layer to indicate transmission data
is available on the TXD.
In RGMII mode, it combines the transmit enable and the transmit error signals
of GMII mode using both clock edges.
GTX_CLK/TCK I 79 GMII and RGMII TRANSMIT CLOCK: This continuous clock signal is sourced
from the MAC layer to the PHY. Nominal frequency is 125 MHz.
TX_ER I 61 TRANSMIT ERROR: It is an active high input used in MII mode and GMII
mode forcing the PHY to transmit invalid symbols. The TX_ER signal is syn-
chronous to the transmit clocks (TX_CLK or GTX_CLK).
In MII 4B nibble mode, assertion of Transmit Error by the controller causes the
PHY to issue invalid symbols followed by Halt (H) symbols until deassertion oc-
curs.
In GMII mode, assertion causes the PHY to emit one or more code-groups that
are invalid data or delimiter in the transmitted frame.
This signal is not used in the RGMII mode.
RX_CLK O_Z 57 RECEIVE CLOCK: Provides the recovered receive clocks for different modes
of operation:
2.5 MHz in 10 Mbps mode.
25 MHz in 100 Mbps mode.
125 MHz in 1000 Mps GMII mode.
This pin is not used in the RGMII mode.
RXD0/RX0
RXD1/RX1
RXD2/RX2
RXD3/RX3
RXD4
RXD5
RXD6
RXD7
O_Z 56
55
52
51
50
47
46
45
RECEIVE DATA: These signals carry 4-bit data nibbles (RXD[3:0]) during 10
Mbps and 100 Mbps MII mode and 8-bit data bytes (RXD[7:0]) in 1000 Mbps
GMII mode. RXD is synchronous to the receive clock (RX_CLK). Receive data
is souirced from the PHY to the MAC layer.
Receive data RX[3:0] is used in RGMII mode. The data is synchronous to the
RGMII receive clock (RCK). The receive data available (RXDV_EN) indicates
valid received data to the MAC layer.
RX_ER/RXDV_ER O_Z 41 RECEIVE ERROR or RECEIVE DATA AVAILABLE/ERROR: In 10 Mbps,
100 Mbps and 1000 Mbps mode this active high output indicates that the PHY
has detected a Receive Error. The RX_ER signal is synchronous with the re-
ceive clock (RX_CLK).
In RGMII mode, the receive data available and receive error is combined
(RXDV_ER) using both rising and falling edges of the receive clock (RCK).
RX_DV/RCK O_Z 44 RECEIVE DATA VALID or RECEIVE CLOCK: In MII and GMII modes, it is as-
serted high to indicate that valid data is present on the corresponding RXD[3:0]
in MII mode and RXD[7:0] in GMII mode.
In RGMII mode, this pin is the recovered receive clock (125MHz).
Signal Name Type
PQFP
Pin #
Description