Datasheet

www.national.com 58
DP83865
4.0 Functional Description (Continued)
after the last bit, carrier sense is de-asserted. Receive
clock stays active for at least five more bit times after CRS
goes low, to guarantee the receive timings of the controller.
The aligned NRZ data is then parallized and aligned to 4-
bit nibbles that is presented to the MII.
4.8.4 Link Detector
In 10 BASE-T mode, the link detection circuit checks for
valid NLP pulses transmitted by the remote link partner. If
valid link pulses are not received the link detector will dis-
able the twisted pair transmitter, receiver and collision
detection functions.
4.8.5 100 BASE-TX ADC Block
The DP83865 requires no external attenuation circuitry at
its receive inputs, MDI+/-. It accepts TP-PMD compliant
waveforms directly from a 1:1 transformer. The analog
MLT-3 signal (with noise and system impairments) is
received and converted to the digital domain via an Analog
to Digital Converter (ADC) to allow for Digital Signal Pro-
cessing (DSP) to take place on the received signal.
4.8.6 BLW / EQ / AAC Correction
The digital data from the ADC block flows into the DSP
Block (BLW/EQ/AAC Correction) for processing. The DSP
block applies proprietary processing algorithms to the
received signal and are all part of an integrated DSP
receiver. The primary DSP functions applied are:
— BLW is defined as the change in the average DC con-
tent, over time, of an AC coupled digital transmission
over a given transmission medium. (i.e. copper wire).
BLW results from the interaction between the low fre-
quency components of a transmitted bit stream and the
frequency response of the AC coupling component(s)
within the transmission system. If the low frequency con-
tent of the digital bit stream goes below the low frequen-
cy pole of the AC coupling transformer then the droop
characteristics of the transformer will dominate resulting
Figure 8. 10BASE-T/100BASE-T Receive Block Diagram
5B/4B DECODER
LOGIC
MDI +/−
RX_CLK
RXD[3:0] /
RX_ER
SERIAL
TO
PARALLEL
DESCRAMB
LER
MLT-3
TO
NRZ
ADC
CLOCK
RECOVERY
DIVIDER
SIGNAL
DETECT
SIGNAL DETECT
RECEIVER
CLOCK &
DATA
RECOVERY
MANCHESTER
TO NRZ
DECODER
AAC
BLW
EQ
CORRECTN
100BASE-TX
10BASE-T
LINK DETECT
LINK
DETECT
4-BIT NIBBLE
DEMUX
RXD[3:0] /
RX_ER
10BASE-T
100BASE-TX