Datasheet

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DP83865
4.0 Functional Description (Continued)
The mapping of the MAC interface is illustrated below in
Table 51.
The GMII interface has the following characteristics:
— Supports 10/100/1000 Mb/s operation
— Data and delimiters are synchronous to clock references
— Provides independent 8-bit wide transmit and receive
data paths
— Provides a simple management interface
— Uses signal levels that are compatible with common
CMOS digital ASIC processes and some bipolar pro-
cesses
— Provides for Full Duplex operation
The GMII interface is defined in the IEEE 802.3z document
Clause 35. In each direction of data transfer, there are Data
(an eight-bit bundle), Delimiter, Error, and Clock signals.
GMII signals are defined such that an implementation may
multiplex most GMII signals with the similar PCS service
interface defined in IEEE 802.3u Clause 22.
Two media status signals are provided. One indicates the
presence of carrier (CRS), and the other indicates the
occurrence of a collision (COL). The GMII uses the MII
management interface composed of two signals (MDC,
MDIO) which provide access to management parameters
and services as specified in IEEE 802.3u Clause 22.
The MII signal names have been retained and the functions
of most signals are the same, but additional valid combina-
tions of signals have been defined for 1000 Mb/s operation.
4.6 Reduced GMII (RGMII)
The Reduced Gigabit Media Independent Interface
(RGMII) is designed to reduce the number of pins required
to interconnect the MAC and PHY (Figure 5). To accom-
plish this goal, the data paths and all associated control
signals are reduced and are multiplexed. Both rising and
trailing edges of the clock are used. For Gigabit operation
the clock is 125 MHz, and for 10 and 100 Mbps operation
the clock frequencies are 2.5 MHz and 25 MHz, respec-
tively. Please refer to the RGMII Specification version 1.3
for detailed descriptions.
4.6.1 1000 Mbps Mode Operation
All RGMII signals are positive logic. The 8-bit data is multi-
plexed by taking advantage of both clock edges. The lower
4 bits are latched on the positive clock edge and the upper
4 bits are latched on trailing clock edge. The control signals
are multiplexed into a single clock cycle using the same
technique.
To reduce power consumption of RGMII interface,
TXEN_ER and RXDV_ER are encoded in a manner that
minimize transitions during normal network operation. This
is done by following encoding method. Note that the value
of GMII_TX_ER and GMII_TX_EN are valid at the rising
edge of the clock. In RGMII mode, GMII_TX_ER is
resented on TXEN_ER at the falling edge of the TCK clock.
RXDV_ER coding is implemented the same fashion.
TXEN_ER <= GMII_TX_ER (XOR) GMII_TX_EN
RXDV_ER <= GMII_RX_ER (XOR) GMII_RX_DV
When receiving a valid frame with no error, “RXDV_ER =
True” is generated as a logic high on the rising edge of
RCK and “RXDV_ER = False” is generated as a logic high
at the falling edge of RCK. When no frame is being
received, “RXDV_ER = False” is generated as a logic low
on the rising edge of RCK and “RXDV_ER = False” is gen-
erated as a logic low on the falling edge of RCK.
When receiving a valid frame with error, “RXDV_ER =
True” is generated as logic high on the rising edge of
RX_CLK and “RXERR = True” is generated as a logic low
on the falling edge of RCK.
TXEN_ER is treated in a similar manner. During normal
frame transmission, the signal stays at a logic high for both
edges of TCK and during the period between frames where
no error is indicated, the signal stays low for both edges.
4.6.2 1000 Mbps Mode Timing
At the time of the publication of RGMII standard version
1.3, there are two different implmentations of RGMII, HP
and 3COM. The difference is in setup and hold timing.
The DP83865 implemented the HP timing. The following is
an explanation of the RGMII interface of the DP83865.
Table 51. GMII/RGMII/MII Mapping
GMII RGMII MII
RXD[3:0] RX[3:0] RXD[3:0]
RXD[4:7]
RX_DV RCK RX_DV
RX_ER RXDV_ER RX_ER
RX_CLK RX_CLK
RGMII_SEL1 TX_CLK
TXD[3:0] TX[3:0] TXD[3:0]
TXD[4:7]
TX_EN TXEN_ER TX_EN
TX_ER TX_ER
GTX_CLK TCK
COL COL
CRS RGMII_SEL0 CRS
Figure 5. RGMII Signals
RGMII
GPHY
TD0
TD1
TD2
TX_CLK
TD3
TXEN_ER
RX_CLK
RD0
RD1
RD2
RD3
RXDV_ER
FUNCTIONAL
BLOCK