Datasheet

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DP83865
PQFP Pin Layout
Figure 1. DP83865 Pinout
Order Part Number: DP83865DVH
MDIA_P
VSS
MDIB_N
1V8_AVDD1
VSS VSS
1V8_AVDD1
VSS VSS VSS VSS VSS VSS
MDIC_P
1V8_AVDD1
MDIA_N
1V8_AVDD1
MDIB_P
MDIC_N
VSS
1V8_AVDD1
VSS VSS
MDID_P
MDID_N
VSS
9
10
11
12
18
22
25
13
16
20
27
29
14
17
23
26
28
30
15
19
21
24
31
32
33
34
35
36
37
38
5
6
7
8
1
2
3
4
59 55 52 64 61 57 50 48 63 60 54 51 49 47 62 58 56 53 46 45 44 43 42 41 40 39
108 112 115 103 106 110 117 119 104 107 113 116 118 120 105 109 111 114 121 122 123 124 125 126 127 128
94
93
92
91
85
81
78
90
87
83
76
74
89
86
80
77
75
73
88
84
82
79
72
71
70
69
68
67
66
65
98
97
96
95
102
101
100
99
LINK100_LED / DUPLEX_STRAP
LINK1000_LED / AN_EN_STRAP
CORE_VDD
VSS
PHYADDR3_STRAP
VSS
CORE_VDD
DUPLEX_LED / PHYADDR0_STRAP
VSS
VSS
TMS
IO_VDD
PHYADDR1_STRAP
PHYADDR2_STRAP
RESERVED
VSS
TDO
VSS
IO_VDD
CORE_VDD
IO_VDD
TCK
TDI
TRST
RESET
VDD_SEL_STRAP
CORE_VDD
VSS
IO_VDD
VSS
VSS
TX_TCLK / MAN_MDIX_STRAP
ACTIVITY_LED / SPEED0_STRAP
LINK10_LED / RLED/SPEED1_STRAP
NON_IEEE_STRAP
RESERVED
INTERRUPT
IO_VDD
MULTI_EN_STRAP / TX_TRIGGER
VSS
CORE_VDD
VSS
CLK_TO_MAC
MDC
VSS
IO_VDD
CLK_OUT
IO_VDD
TXD0/TX0
VSS
MDIX_EN_STRAP
CLK_IN
MDIO
IO_VDD
TXD1/TX1
CORE_VDD
MAC_CLK_EN_STRAP
RESERVED
VSS
GTX_CLK/TCK
TXD2/TX2
TXD3/TX3
VSS
IO_VDD
TXD4
TXD5
TXD6
TXD7
1V8_AVDD2
VSS
2V5_AVDD2
PHYADDR4_STRAP
BG_REF
2V5_AVDD1
1V8_AVDD3
VSS
VSS RXD1/RX1 RXD2/RX2 VSS TX_ER RX_CLK RXD4 CORE_VDD CORE_VDD TX_CLK/RGMII_SEL1 VSS RXD3/RX3 VSS RXD5 TX_EN/TXEN_ER IO_VDD RXD0/RX0 IO_VDD RXD6 RXD7 RX_DV/RCK VSS IO_VDD RX_ER/RXDV_ER CRS/RGMII_SEL0 COL/CLK_MAC_FREQ
DP83865DVH
Gig PHYTER V