Datasheet

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DP83865
2.0 Register Block (Continued)
Table 28. PHY Support Register #2 (PHY_SUP) address 0x1F (31’d)
Bit Bit Name Default Description
15:5 Reserved 0, RO Write as 0, ignore on read.
4:0 PHY Address STRAP[0_0001],
RW
PHY Address: Defines the port on which the PHY will accept Se-
rial Management accesses.