Datasheet
3 www.national.com
Table of Contents
1.0 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.1 MAC Interfaces (MII, GMII, and RGMII) . . . . . . . 5
1.2 Management Interface . . . . . . . . . . . . . . . . . . . . 7
1.3 Media Dependent Interface . . . . . . . . . . . . . . . . 7
1.4 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.5 Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.6 Device Configuration and LED Interface . . . . . . . . 8
1.7 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.8 Power and Ground Pins . . . . . . . . . . . . . . . . . . . . 11
1.9 Special Connect Pins . . . . . . . . . . . . . . . . . . . . 11
1.10 Pin Assignments in the Pin Number Order . . . . 12
2.0 Register Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.1 Register Definitions . . . . . . . . . . . . . . . . . . . . . . . 18
2.2 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3 Register Description . . . . . . . . . . . . . . . . . . . . . . 21
3.0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.1 Accessing Expanded Memory Space . . . . . . . . . 40
3.2 Manual Configuration . . . . . . . . . . . . . . . . . . . . . . 40
3.3 Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.4 Auto-Negotiation Register Set . . . . . . . . . . . . . . . 44
3.5 Auto-MDIX resolution . . . . . . . . . . . . . . . . . . . . . . 44
3.6 Polarity Correction . . . . . . . . . . . . . . . . . . . . . . . . 45
3.7 PHY Address, Strapping Options and LEDs . . . . 45
3.8 Reduced LED Mode . . . . . . . . . . . . . . . . . . . . . . 45
3.9 Modulate LED on Error . . . . . . . . . . . . . . . . . . . . 45
3.10 MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.11 Clock to MAC Enable . . . . . . . . . . . . . . . . . . . . . . 46
3.12 MII/GMII/RGMII Isolate Mode . . . . . . . . . . . . . . . 46
3.13 Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.14 IEEE 802.3ab Test Modes . . . . . . . . . . . . . . . . . . 46
3.15 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.16 Low Power Mode / WOL . . . . . . . . . . . . . . . . . . . 47
3.17 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . 47
3.18 BIST Configuration . . . . . . . . . . . . . . . . . . . . . . . 47
3.19 Cable Length Indicator . . . . . . . . . . . . . . . . . . . . . 48
3.20 10BASE-T Half Duplex Loopback . . . . . . . . . . . . 48
3.21 I/O Voltage Selection . . . . . . . . . . . . . . . . . . . . . . 48
3.22 Non-compliant inter-operability mode . . . . . . . . . 48
4.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.1 1000BASE-T PCS Transmitter . . . . . . . . . . . . . . 49
4.2 1000BASE-T PMA Transmitter . . . . . . . . . . . . . . 50
4.3 1000BASE-T PMA Receiver . . . . . . . . . . . . . . . . 50
4.4 1000BASE-T PCS Receiver . . . . . . . . . . . . . . . . 51
4.5 Gigabit MII (GMII) . . . . . . . . . . . . . . . . . . . . . . . . 52
4.6 Reduced GMII (RGMII) . . . . . . . . . . . . . . . . . . . . 53
4.7 10BASE-T and 100BASE-TX Transmitter . . . . . . 54
4.8 10BASE-T and 100BASE-TX Receiver . . . . . . . . 57
4.9 Media Independent Interface (MII) . . . . . . . . . . . .60
5.0 Design Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.1 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.3 Power Supply Decoupling . . . . . . . . . . . . . . . . . . 64
5.4 Sensitive Supply Pins . . . . . . . . . . . . . . . . . . . . . 64
5.5 PCB Layer Stacking . . . . . . . . . . . . . . . . . . . . . . . 64
5.6 Layout Notes on MAC Interface . . . . . . . . . . . . . . 66
5.7 Twisted Pair Interface . . . . . . . . . . . . . . . . . . . . . 66
5.8 RJ-45 Connections . . . . . . . . . . . . . . . . . . . . . . . 67
5.9 LED/Strapping Option . . . . . . . . . . . . . . . . . . . . . 67
5.10 Unused Pins and Reserved Pins . . . . . . . . . . . . . 67
5.11 I/O Voltage Considerations . . . . . . . . . . . . . . . . . 68
5.12 Power-up Recommendations . . . . . . . . . . . . . . . 68
5.13 Component Selection . . . . . . . . . . . . . . . . . . . . . 68
6.0 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . 71
6.1 DC Electrical Specification . . . . . . . . . . . . . . . . . 71
6.2 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.3 Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.4 1000 Mb/s Timing . . . . . . . . . . . . . . . . . . . . . . . . 74
6.5 RGMII Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.6 100 Mb/s Timing . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.7 10 Mb/s Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.8 Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . 79
6.9 Serial Management Interface Timing . . . . . . . . . 80
6.10 Power Consumption . . . . . . . . . . . . . . . . . . . . . . 81
7.0 Frequently Asked Questions . . . . . . . . . . . . . . . . . . . 82
7.1 Do I need to access any MDIO register to start up
the PHY? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
7.2 I am trying to access the registers through MDIO
and I got invalid data. What should I do? . . . . . 82
7.3 Why can the PHY establish a valid link but can
not transmit or receive data? . . . . . . . . . . . . . . . 82
7.4 What is the difference between TX_CLK,
TX_TCLK, and GTX_CLK? . . . . . . . . . . . . . . . . 82
7.5 What happens to the TX_CLK during 1000 Mbps
operation? Similarly what happens to RXD[4:7]
during 10/100 Mbps operation? . . . . . . . . . . . . . 82
7.6 What happens to the TX_CLK and RX_CLK
during Auto-Negotiation and during idles? . . . . . 82
7.7 Why doesn’t the Gig PHYTER V complete Auto-
Negotiation if the link partner is a forced
1000 Mbps PHY? . . . . . . . . . . . . . . . . . . . . . . . . 82
7.8 What determines Master/Slave mode when Auto-
Negotiation is disabled in 1000Base-T mode? . . 82
7.9 How long does Auto-Negotiation take? . . . . . . . 83
7.10 How do I measure FLP’s? . . . . . . . . . . . . . . . . . 83
7.11 I have forced 10 Mbps or 100 Mbps operation but
the associated speed LED doesn’t come on. . . . 83
7.12 I know I have good link, but register 0x01, bit 2
“Link Status” doesn’t contain value ‘1’ indicating
good link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.13 Your reference design shows pull-up or pull-down
resistors attached to certain pins, which conflict
with the pull-up or pull-down information specified
in the datasheet? . . . . . . . . . . . . . . . . . . . . . . . . 83
7.14 How is the maximum package case temperature
calculated? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.15 The DP83865 will establish Link in 100 Mbps
mode with a Broadcom part, but it will not
establish link in 1000 Mbps mode. When this
happens the DP83865’s Link LED will blink on
and off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.16 How do I quickly determine the quality of the
link over the cable ? . . . . . . . . . . . . . . . . . . . . . . 83
7.17 What is the power up sequence for DP83865? . 83
7.18 What are some other applicable documents? . . 84
8.0 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 86