Datasheet

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DP83865
2.0 Register Block (Continued)
Note: Registers 0x1B and 0x1C are reserved.
10 tx_bist_pak_type 0, RW Transmit BIST Packet Type:
1 = PSR9
0 = User defined packet
9:8 Reserved 0, RO Write as 0, ignore on read.
7:0 tx_bist_pak 0, RW User Defined Packet Content: This field sets the packet content
for the transmit BIST packets if the user defined packet type in bit
10 is selected.
Table 25. BIST Configuration Register 2 (BIST_CFG2) address 0x1A (26’d)
Bit Bit Name Default Description
15 rx_bist_en 0, RW Receive BIST Enable: This bit enables the receive BIST
counter. The BIST counter operation does not interfere with nor-
mal PHY operation.
0 = BIST counter disabled
1 = BIST counter enabled
14 bist_cnt_sel 0, RW BIST Counter Select: This bit selects whether the upper or lower
16 bit of the 32 bit counter value are shown in the BIST_CNT reg-
ister.
0 = displays lower 16 bit
1 = displays upper 16 bit
13:11 tx_bist_pak_cnt 0, RW Transmit BIST Packet Count: Sets the number of transmit pack-
ets
000 = continuous transmit
001 = 1 packet
010 = 10 packets
011 = 100 packets
100 = 1,000 packets
101 = 10,000 packets
110 = 100,000 packets
111 = 10,000,000 packets
10:1 Reserved 0, RO Write as 0, ignore on read.
0 Link/Link-ACT sel 0, RW Link/Link-ACT Select: This bit has no impact when Reg 0x13.5
= 0.
1 = LINK only
0 = Combined Link/ACT
Table 24. BIST Configuration Register 1 (BIST_CFG1) address 0x19 (25’d)
Bit Bit Name Default Description
Table 26. Expanded Memory Data Register (Exp_mem_data) address 0x1D (29’d)
Bit Bit Name Default Description
15:0 Expanded Memory
Data
0, RW Expanded Memory Data: Data to be written to or read from ex-
panded memory. Note that in 8-bit mode, the data resides at the
LSB octet of this register.
Table 27. Expanded Memory Address Register (Exp_mem_addr) address 0x1E (30’d)
Bit Bit Name Default Description
15:0 Expanded Memory
Address
0, RW Expanded Memory Address: Pointer to the address in expand-
ed memory. The pointer is 16-bit wide.