Datasheet

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DP83865
2.0 Register Block (Continued)
Table 22. Interrupt Clear Register (INT_CLEAR) address 0x17 (23’d)
Bit Bit Name Default Description
15 spd_cng_int_clr 0, RW, SC Setting this bit clears the spd_cng_int interrupt.
14 lnk_cng_int_clr 0, RW, SC Setting this bit clears the lnk_cng_int interrupt.
13 dplx_cng_int_clr 0, RW, SC Setting this bit clears the dplx_cng_int interrupt.
12 mdix_cng_int_clr 0, RW, SC Setting this bit clears the mdix_cng_int interrupt.
11 pol_cng_int_clr 0, RW, SC Setting this bit clears the pol_cng_int interrupt.
10 prl_det_flt_int_clr 0, RW, SC Setting this bit clears the prl_det_flt_int interrupt.
9 mas_sla_err_int_clr 0, RW, SC Setting this bit clears the mas_sla_err_int interrupt.
8 no_hcd_int_clr 0, RW, SC Setting this bit clears the no_hcd_int interrupt.
7 no_lnk_int_clr 0, RW, SC Setting this bit clears the no_lnk_int interrupt.
6 jabber_cng_int_clr 0, RW, SC Setting this bit clears the jabber_cng_int interrupt.
5 nxt_pg_rcvd_int_clr 0, RW, SC Setting this bit clears the nxt_pg_rcvd_int interrupt.
4 an_cmpl_int_clr 0, RW, SC Setting this bit clears the an_cmpl_int interrupt.
3 rem_flt_cng_int_clr 0, RW, SC Setting this bit clears the rem_flt_cng_int interrupt.
2:0 Reserved 0, RO Write as 0, ignore on read.
Table 23. BIST Counter Register (BIST_CNT) address 0x18 (24’d)
Bit Bit Name Default Description
15:0 BIST Counter 0, RO BIST Counter: This register counts receive packets or receive
errors according to bit 15 in register BIST_CFG1. It shows either
the upper or lower 16 bit of a 32 bit value which can be selected
through bit 14 in register BIST_CFG2.
Table 24. BIST Configuration Register 1 (BIST_CFG1) address 0x19 (25’d)
Bit Bit Name Default Description
15 bist_cnt_type 0, RW Set BIST Counter Type:
1 = BIST_CNT counts receive CRC errors
0 = BIST_CNT counts receive packets
14 bist_cnt_clr 0, RW, SC BIST Counter Clear: Setting this bit clears the BIST_CNT regis-
ter to 0.
13 tx_bist_pak_len 0, RW Transmit BIST Packet Length:
1 = 1514 bytes
0 = 60 bytes
12 tx_bist_ifg 0, RW Transmit BIST Interframe Gap: This bit sets the IFG for transmit
BIST packets.
1 = 9.6 us
0 = 0.096us
11 tx_bist_en 0, RW, SC Transmit BIST Enable: This bit starts the transmit BIST. The
number of selected packets or a continous data stream is sent out
when set. This bit self-clears after the packets have been sent.
1 = Transmit BIST enabled
0 = Transmit BIST disabled