Datasheet

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DP83865
2.0 Register Block (Continued)
Table 20. Interrupt Mask Register (INT_MASK) address 0x15 (21’d)
Bit Bit Name Default Description
15 spd_cng_int_msk 0, RW Setting this bit activates the spd_cng_int interrupt. The interrupt
is masked if the bit is cleared.
14 lnk_cng_int_msk 0, RW Setting this bit activates the lnk_cng_int interrupt. The interrupt is
masked if the bit is cleared.
13 dplx_cng_int_msk 0, RW Setting this bit activates the dplx_cng_int interrupt. The interrupt
is masked if the bit is cleared.
12 mdix_cng_int_msk 0, RW Setting this bit activates the mdix_cng_int interrupt. The interrupt
is masked if the bit is cleared.
11 pol_cng_int_msk 0, RW Setting this bit activates the pol_cng_int interrupt. The interrupt is
masked if the bit is cleared.
10 prl_det_flt_int_msk 0, RW Setting this bit activates the prl_det_flt_int interrupt. The interrupt
is masked if the bit is cleared.
9 mas_sla_err_int_msk 0, RW Setting this bit activates the mas_sla_err_int interrupt. The inter-
rupt is masked if the bit is cleared.
8 no_hcd_int_msk 0, RW Setting this bit activates the no_hcd_int interrupt. The interrupt is
masked if the bit is cleared.
7 no_lnk_int_msk 0, RW Setting this bit activates the no_lnk_int interrupt. The interrupt is
masked if the bit is cleared.
6 jabber_cng_int_msk 0, RW Setting this bit activates the jabber_cng_int interrupt. The inter-
rupt is masked if the bit is cleared.
5 nxt_pg_rcvd_int_msk 0, RW Setting this bit activates the nxt_pg_rcvd_int interrupt. The inter-
rupt is masked if the bit is cleared.
4 an_cmpl_int_msk 0, RW Setting this bit activates the an_cmpl_int interrupt. The interrupt
is masked if the bit is cleared.
3 rem_flt_cng_int_msk 0, RW Setting this bit activates the rem_flt_cng_int interrupt. The inter-
rupt is masked if the bit is cleared.
2:0 Reserved 0, RO Write as 0, ignore on read.
Table 21. Expanded Memory Access Control (Exp_mem_ctl) address 0x16 (22’d)
Bit Bit Name Default Description
15 Global Reset 0, RW, SC Global Reset:
This bit resets the entire chip.
14:8 Reserved 0, RO Write as 0, ignore on read.
7 Broadcast Enable 0, RW Broadcast Enable:
1 = Respond to broadcast write at MDIO address 0
0 = Respond to MDIO address set in register 0x1F.4:0
6:2 Reserved 0, RO Write as 0, ignore on read.
1:0 Address Control [11], RW Address Control:
00 = 8-bit expanded memory read/write (auto-incr disabled)
01 = 8-bit expanded memory read/write (auto-incr enabled)
10 = 16-bit expanded memory read/write (auto-incr enabled)
11 = 8-bit expanded memory write-only (auto-incr disabled)