Datasheet
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DP83865
2.0 Register Block (Continued)
5 Shallow Deep Loop-
back
Enable
0, RW Shallow Deep Loopack Enable: (Loopback status bit 7, register
0x11)
This bit places PHY in the MAC side loopback mode. Any packet
entering into TX side appears on the RX pins immediately. This
operation bypasses all internal logic and packet does not appear
on the MDI interface.
1 = The PHY operates in shallow deep loopback mode
0 = Normal operation
4 X_Mac 0, RW Reverse GMII Data Bit Order:
Setting this bit will reverse the pins of the TXD and RXD on the
GMII interface, respectively.
1 = TXD[7:0]=>TXD[0:7], RXD[7:0]=>RXD[0:7]
0 = Normal operation
3:1 Reserved 0, RO Write as 0, ignore on read.
0 Jabber Disable 0, RW Jabber Disable: (Only in 10BASE-T mode) If this bit is set the
PHY ignores all jabber conditions.
1 = disable jabber function
0 = normal operation
Table 18. LED Control Register (LED_CTRL) address 0x13 (19’d)
Bit Bit Name Default Description
15:14 Activity LED 0, RW Activity LED: This LED is active when the PHY is transmitting
data, receiving data, or detecting idle error.
The following modes are available for the ACT LED:
00 = Register controlled 0x13.3:0
01 = Forced off
10 = Blink mode (blink rate approx. 750 ms)
11 = Forced on
Note: Only in normal mode (00) LEDs reflect the actual status of
the PHY. All other modes force the driver to a permanent on, off
or blinking state.
13:12 Link10 LED 0, RW 10BASE-T Link LED: This LED is active when the PHY is linked
in 10BASE-T mode.
The following modes are available for LEDs:
00 = Normal (default)
01 = Forced off
10 = Blink mode (blink rate approx. 750 ms)
11 = Forced on
Note: Only in normal mode (00) LEDs reflect the actual status of
the PHY. All other modes force the driver to a permanent on, off
or blinking state.
11:10 Link100 LED 0, RW 100BASE-TX Link LED: This LED is active when the PHY is
linked in 100BASE-TX mode. See Activity LED for other settings.
9:8 Link1000 LED 0, RW 1000BASE-T Link LED: This LED is active when the PHY is
linked in 1000BASE-T mode. See Activity LED for other settings.
7:6 Duplex LED 0, RW Duplex LED: This LED is active when the PHY has established
a link in Full Duplex mode. See Activity LED for other settings.
Table 17. Auxiliary Control Register (AUX_CTRL) address 0x12 (18’d)
Bit Bit Name Default Description