Datasheet

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DP83865
2.0 Register Block (Continued)
Table 17. Auxiliary Control Register (AUX_CTRL) address 0x12 (18’d)
Bit Bit Name Default Description
15 Auto-MDIX Enable STRAP[1], RW Automatic MDIX: Indicates (sets) whether the PHY’s capability
to automatically detect swapped cable pairs is used.
1 = Automatic MDIX mode, bit 14 is ignored
0 = Manual MDIX mode
Note: This bit is ignored and the setting of bit 14 applies if Auto-
Negotiation is disabled (AN_EN = 0). Bit 10 of register 0x11
should always be checked for the actual status of MDI/MDIX op-
eration.
14 Manual MDIX Value STRAP[0], RW Manual MDIX Value: If Manual MDIX mode is selected (Auto-
MDIX selection is disabled, bit 15 = 0) this bit sets the MDIX
mode of operation. If the PHY is in Auto-MDIX mode this bit has
no effect.
1 = cross-over mode (channels A and B are swapped)
0 = straight mode
Note: Bit 10 of register 0x11 should always be checked for the ac-
tual status of MDI/MDIX operation.
13:12 RGMII_EN[1:0] STRAP[0] RGMII ENABLE: These two bits enables RGMII mode or
MII/GMII mode.
RGMII_EN[1:0]
11 = RGMII - 3COM mode
10 = RGMII - HP mode
01 = GMII mode
00 = GMII mode
11:10 Reserved 0, RO Write as 0, ignore on read.
9 Non-Compliant Mode STRAP[0], RW Non-Compliant Mode Enable: This bit enables the PHY to work
in non-IEEE compliant mode. This allows interoperabilty with cer-
tain non-IEEE compliant 1000BASE-T tranceivers.
1 = enables IEEE compliant operation and non-compliant opera-
tion
0 = enables IEEE compliant operation but inhibits non-compliant
operation
8 RGMII InBand
Status Enable
0, RW RGMII InBand Status Enable:
1 = RGMII InBand Status enabled.
0 = RGMII InBand Status disabled.
When InBand Status is enabled, PHY places link status, speed,
and duplex mode information on RXD[3:0] between the data
frames. The InBand Status may ease the MAC layer design.
Note that this bit has no impact if bit 13 = 0.
7 TX_TCLK Enable 0, RW TX_TCLK Enable: This bit enables the TX_TCLK (pin 6) output
during the IEEE 1000BASE-T test modes.
1 = TX_TCLK ouput enabled during IEEE test modes
0 = No TX_TCLK output (default)
6 TX_Trigger_Syn
Enable
0, RW TX_TRIGGER and TX_SYNC Enable: This bit enables the
TX_SYNC_CLK (pin 88) and TX_TRIGGER (pin 94) output dur-
ing the IEEE 1000BASE-T modes. These signals are not required
by IEEE to perform the tests, but will help to take measurements.
0 = No signal output
1 = Signal are output during IEEE test modes
Note: TX_SYN_CLK and TX_TRIGGER are only available in test
mode 1 and 4
TX_SYN_CLK = TX_TCLK / 4 in test mode 1
TX_SYN_CLK = TX_TCLK / 6 in test mode 4