Datasheet
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DP83865
2.0 Register Block (Continued)
This register summarizes all the strap options. These can only be changed through restrapping and resetting the PHY.
Table 14. 1000BASE-T Extended Status Register (1KSCR) address 0x0F (15’d)
Bit Bit Name Default Description
15 1000BASE-X
Full Duplex
0, P 1000BASE-X Full Duplex Support:
1 = 1000BASE-X is supported by the local device.
0 = 1000BASE-X is not supported.
DP83865 does not support 1000BASE-X and bit should always
be read back as “0”.
14 1000BASE-X
Half Duplex
0, P 1000BASE-X Half Duplex Support:
1 = 1000BASE-X is supported by the local device.
0 =1000BASE-X is not supported.
DP83865 does not support 1000BASE-X and bit should always
be read back as “0”.
13 1000BASE-T
Full Duplex
1, P 1000BASE-T Full Duplex Support:
1 = 1000BASE-T is supported by the local device.
0 =1000BASE-T is not supported.
12 1000BASE-T
Half Duplex
1, P 1000BASE-T Half Duplex Support:
1 = 1000BASE-T is supported by the local device.
0 =1000BASE-T is not supported.
11:0 Reserved 0, RO Reserved by IEEE: Write ignored, read as 0.
Table 15. Strap Option Register (STRAP_REG) address 0x10 (16’d)
Bit Bit Name Default Description
15 AN Enable STRAP[1], RO Auto-Negotiation Enable: Pin 10. Default value for bit 12 of reg-
ister 0x00.
14 Duplex Mode STRAP[1], RO Duplex Mode: Pin 9. Default value for bit 8 of register 0x00.
13:12 Speed[1:0] STRAP[00], RO Speed Select: Pins 8 and 7. Default value for bits 6 and 13 of reg-
ister 0x00.
11 Reserved 0, RO Write as 0, ignore on read.
10 NC Mode Enable STRAP[0], RO Non-Compliant Mode: Pin 1. Default value for bit 9 of register
0x12.
9 Reserved 0, RO Write as 0, ignore on read.
8 Reserved 0, RO Write as 0, ignore on read.
7 MAC Clock Enable STRAP[1], RO MAC Clock Output Enable: Pin 88.
6 MDIX Enable STRAP[1], RO Auto MDIX Enable: Pin 89. Default value for bit 15 of register
0x12.
5 Multi Enable STRAP[0], RO Multi Port Enable: Pin 94. Default value for bit 10 of register
0x09.
4:0 PHYADDR[4:0] STRAP[0_0001],
RO
PHY Address: Pins 95, 18, 17,14, 13. Default for bits 4:0 of reg-
ister 0x1F.