Datasheet

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DP83865
Block Diagram
100BASE-TX
PCS
100BASE-TX
PMA
100BASE-TX
PMD
1000BASE-T
PCS
1000BASE-T
PMA
DAC/ADC
SUBSYSTEM
DRIVERS/
RECEIVERS
MAGNETICS
MLT-3
100 Mb/s
PAM-5
17 Level PR Shaped
125 Msymbols/s
4-pair CAT-5 Cable
MII
GMII
COMBINED MII / GMII / RGMII INTERFACE
1000BASE-T
µC MGMT
& PHY CNTRL
TIMING
GTX_CLK TX_EN TXD[7:0] TX_CLK RX_CLK COL CRS RX_ER RX_DV RXD[7:0]
DAC/ADC
TIMING BLOCK
100BASE-TX
GMIIMII
MUX/DMUX
MGMT INTERFACE
TX_ER
10BASE-T
10BASE-T
PLS
10BASE-T
PMA
Manchester
10 Mb/s
MII
MDIO MDC Interrupt
Echo cancellation
Crosstalk cancellation
ADC
Decode/Descramble
Equalization
Timing
Skew compensation
BLW
Block Block Block