Datasheet

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DP83865
2.0 Register Block (Continued)
11 Power_Down 0, RW Power Down:
1 = Power down (only Management Interface and logic active.)
0 = Normal operation.
Note: This mode is internally the same as isolate mode (bit 10).
10 Isolate 0, RW Isolate:
1 = Isolates the Port from the MII/GMII with the exception of the
serial management. When this bit is asserted, the DP83865 does
not respond to TXD[7:0], TX_EN, and TX_ER inputs, and it pre-
sents a high impedance on TX_CLK, RX_CLK, RX_DV, RX_ER,
RXD[7:0], COL and CRS outputs.
0 = Normal operation.
9 Restart_AN 0, RW, SC Restart Auto-Negotiation:
1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation
process. If Auto-Negotiation is disabled (bit 12 = 0), this bit is ig-
nored. This bit is self-clearing and will return a value of 1 until
Auto-Negotiation is initiated, whereupon it will self-clear. Opera-
tion of the Auto-Negotiation process is not affected by the man-
agement entity clearing this bit.
0 = Normal operation.
8 Duplex STRAP[1], RW Duplex Mode:
1 = Full Duplex operation. Duplex selection is allowed only
when
Auto-Negotiation is disabled (AN_EN = 0).
0 = Half Duplex operation.
(The default value of this bit is = to the strap value of pin 9 during
reset/power-on IF Auto-Negotiation is disabled.)
7 Collision Test 0, RW Collision Test:
1 = Collision test enabled.
0 = Normal operation.
When set, this bit will cause the COL signal to be asserted in re-
sponse to the assertion of TX_EN withinTBD-bit times. The COL
signal will be de-asserted within 4-bit times in response to the de-
assertion of TX_EN.
6 Speed[1] STRAP[0], RW Speed Select: See description for bit 13.
(The default value of this bit is = to the strap value of pin 8 during
reset/power-on IF Auto-Negotiation is disabled.)
5:0 Reserved 0, RO Reserved by IEEE: Write ignored, read as 0.
Table 3. Basic Mode Control Register (BMCR) address 0x00
Bit Bit Name Default Description
Table 4. Basic Mode Status Register (BMSR) address 0x01
15 100BASE-T4 0, P 100BASE-T4 Capable:
0 = Device not able to perform 100BASE-T4 mode.
DP83865 does not support 100BASE-T4 mode and bit should al-
ways be read back as “0”.
14 100BASE-X
Full Duplex
1, P 100BASE-X Full Duplex Capable:
1 = Device able to perform 100BASE-X in Full Duplex mode.
13 100BASE-X
Half Duplex
1, P 100BASE-X Half Duplex Capable:
1 = Device able to perform 100BASE-X in Half Duplex mode.