Datasheet

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DP83865
2.0 Register Block (Continued)
Register Name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register 0x10 (16’d) Strap Option Register (STRAP_REG)
AN Enable
STRAP[1]
Full Duplex
Enable
STRAP[1]
Speed[1]
STRAP[0]
Speed[0]
STRAP[0]
Reserved
(REF_SEL)
STRAP[0]
NC Mode
STRAP[0]
Reserved
(REF_SEL)
STRAP[0]
Reserved
(REF_SEL)
STRAP[0]
MAC Clock
Enable
STRAP[1]
Auto MDIX
Enable
STRAP[1]
Multi Enable
STRAP[0]
PHYADDR[4]
STRAP[0]
PHYADDR[3]
STRAP[0]
PHYADDR[2]
STRAP[0]
PHYADDR[1]
STRAP[0]
PHYADDR[0]
STRAP[1]
Register 0x11 (17’d) Link and Auto-Negotiation
Status Register (LINK_AN)
TP_POL[3]
0
TP_POL[2]
0
TP_POL[1]
0
TP_POL[0]
0
Reserved
(Power Down
Status)
0
MDIX Status
0
FIFO Error
0
Reserved
(Power-On Init
In Progress)
0
Reserved
(Shallow Loop-
back Status
0
(Deep) Loop-
back
Status
0
NC Mode
Status
0
Speed
Status[1]
0
Speed
Status[0]
0
Link Status
0
Duplex Status
0
Master/Slave
Config. Status
0
Register 0x12 (18’d) Auxiliary Control Register (AUX_CTRL)
Auto MDIX
Enable
STRAP[1]
Manual MDIX
Mode
STRAP[0]
RGMII_EN[1]
STRAP[0]
RGMII_EN[0]
STRAP[0]
Reserved
(RGMII Inband
Sig. Enable)
0
Reserved
(RGMII Inband
Sig. Enable)
0
NC Mode
Enable
STRAP[0]
RGMII_inband
Status Enable
0
TX_TCLK
Enable
0
TX_TRIG
/SYNC Enable
0
Shallow Loop-
back Enable
0
X_Mac Enable
0
Reserved
0
Reserved
0
Reserved
0
Jabber Disable
0
Register 0x13 (19’d) LED Control Register (LED_CTRL)
Act. LED[1]
0
Act. LED[0]
0
10BASE-T
Link LED[1]
0
10BASE-T
Link LED[0]
0
100BASE-TX
Link LED[1]
0
100BASE-TX
Link LED[0]
0
1000BASE-T
Link LED[1]
0
1000BASE-T
Link LED[0]
0
Duplex LED[1]
0
Duplex LED[0]
0
10M LED
RLED enable
0
Modulate LED
on CRC Error
0
Modulate LED
on Idle Error
0
AN Fallback
on Gigabit Link
0
AN Fallback
on CRC Error
0
AN Fallback
on Idle Error
0
Register 0x14 (20’d) Interrupt Status Register (INT_STATUS)
Speed Change
Int.
0
Link Change
Int.
0
Duplex
Change Int.
0
MDIX Change
Int.
0
Polarity
Change Int.
0
PDF Detection
Fault Int.
0
Master/Slave
Fail Int.
0
No HCD Int.
0
No Link Int.
0
Jabber Change
Int.
0
Next Page
Received Int.
0
Auto-Neg.
Complete Int.
0
Remote Fault
Change Int.
0
Reserved
0
Reserved
0
Reserved
0
Register 0x15 (21’d) Interrupt Mask Register (INT_MASK)
Mask Int.
0
Mask Int.
0
Mask Int.
0
Mask Int.
0
Mask Int.
0
Mask Int.
0
Mask Int.
0
Mask Int.
0
Mask Int.
0
Mask Int.
0
Mask Int.
0
Mask Int.
0
Mask Int.
0
Reserved
0
Reserved
0
Reserved
0
Register 0x16 (22’d) Exp Memory Access Control (EXP_MEM_CTL)
Global Reset
0, SC
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
(Broadcast En-
able)
0
Broadcast En.
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
XMode[1]
0
XMode[0]
0
Register 0x17 (23’d) Interrupt Clear Register (INT_CLEAR)
Clear Int.
0, SC
Clear Int.
0, SC
Clear Int.
0, SC
Clear Int.
0, SC
Clear Int.
0, SC
Clear Int.
0, SC
Clear Int.
0, SC
Clear Int.
0, SC
Clear Int.
0, SC
Clear Int.
0, SC
Clear Int.
0, SC
Clear Int.
0, SC
Clear Int.
0, SC
Reserved
0
Reserved
0
Reserved
0
Register 0x18 (24’d) BIST Counter Register (BIST_CNT)
Counter Bit[15]
0
Counter Bit[14]
0
Counter Bit[13]
0
Counter Bit[12]
0
Counter Bit[11]
0
Counter Bit[10]
0
Counter Bit[9]
0
Counter Bit[8]
0
Counter Bit[7]
0
Counter Bit[6]
0
Counter Bit[5]
0
Counter Bit[4]
0
Counter Bit[3]
0
Counter Bit[2]
0
Counter Bit[1]
0
Counter Bit[0]
0
Register 0x19 (25’d) BIST Configuration Register
#1 (BIST_CFG1)
BIST Counter
Type
0
BIST Counter
Clear
0
Transmit BIST Packet Length
0
Transmit BIST
IFG
0
Transmit BIST
Enable
0
Transmit BIST
Packet Type
0
Reserved
0
Reserved
0
Transmit BIST
Packet[7]
0
Transmit BIST
Packet[6]
0
Transmit BIST
Packet[5]
0
Transmit BIST
Packet[4]
0
Transmit BIST
Packet[3]
0
Transmit BIST
Packet[2]
0
Transmit BIST
Packet[1]
0
Transmit BIST
Packet[0]
0
Register 0x1A (26’d) BIST Configuration Register
#2 (BIST_CFG2)
Receive BIST
Enable
0
BIST Counter
Select
0
Transmit BIST
Packet
Count[2]
0
Transmit BIST
Packet
Count[1]
0
Transmit BIST
Packet
Count[0]
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
10M LED
ACT/LNK-LNK
0
Register 0x1B (27’d) Reserved
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Register 0x1C (28’d) Reserved
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Register 0x1D (29’d) Exp Memory Data (EXP_MEM_DATA)
Exp Mem Data
15
0
Exp Mem Data
14
0
Exp Mem Data
13
0
Exp Mem Data
12
0
Exp Mem Data
11
0
Exp Mem Data
10
0
Exp Mem Data
9 0
Exp Mem Data
8 0
Exp Mem Data
7 0
Exp Mem Data
6 0
Exp Mem Data
5 0
Exp Mem Data
4 0
Exp Mem Data
3 0
Exp Mem Data
2 0
Exp Mem Data
1 0
Exp Mem Data
0 0
Register 0x1E (30’d) Exp Memory Address Pointer (EXP_MEM_ADD)
Exp Mem Addr
15
0
Exp Mem Addr
14
0
Exp Mem Addr
13
0
Exp Mem Addr
12
0
Exp Mem Addr
11
0
Exp Mem Addr
10
0
Exp Mem Addr
9 0
Exp Mem Addr
8 0
Exp Mem Addr
7 0
Exp Mem Addr
6 0
Exp Mem Addr
5 0
Exp Mem Addr
4 0
Exp Mem Addr
3 0
Exp Mem Addr
2 0
Exp Mem Addr
1 0
Exp Mem Addr
0 0
Register 0x1F (31’d) PHY Support Register (PHY_SUP)
Reserved
0
Reserved
0
Reserved
0
Reserved
BrdCst_AD[4]
0
Reserved
BrdCst_AD[3]
0
Reserved
BrdCst_AD[2]
0
Reserved
BrdCst_AD[1]
0
Reserved
BrdCst_AD[0]
0
Reserved
0
Reserved
0
Reserved
0
PHY
ADDRESS[4]
0
PHY
ADDRESS[3]
0
PHY
ADDRESS[2]
0
PHY
ADDRESS[1]
0
PHY
ADDRESS[0]
1
Key: Bit Name
Read/Writable
Default Value
Bit Name
Read Only
Value
Reserved