Datasheet

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DP83865
1.0 Pin Description (Continued)
79 GTX_CLK/TCK Input GMII Transmit Clock: Connect to MAC chip
through a single 50 Ω impedance trace. This in-
put has a typical input capacitance of 6 pF
80 MDIO Input /
Output
Management Data I/O: This pin requires a 2kΩ
parallel termination resistor (pull-up to VDD).
81 MDC Input Management Data Clock: Connect to MAC or
controller using a 50 Ω impedance trace.
82 VSS Ground Ground: Connect to common ground plane.
83 IO_VDD Power I/O VDD: (Digital) Connect to 2.5V or 3.3V. The
VDD_SEL pin must be tied accordingly.
84 RESERVED Reserved Reserved: Leave floating.
85 CLK_TO_MAC Output Clock to MAC: Connect to the reference clock
input of a GMAC. Use pin
MAC_CLK_EN_STRAP to disable this function.
86 CLK_IN Input Clock Input: Connect to external 25MHz refer-
ence clock source. If a crystal is used connect to
first terminal of crystal.
87 CLK_OUT Input Clock Output: Connect to the second terminal
of a crystal. Leave floating if an external clock
source is used.
88 MAC_CLK_EN_STRAP Strap Clock to MAC Enable: Use a 2kΩ pull-down re-
sistor to disable. Leave open to enable.
89 MDIX_EN_STRAP Strap Automatic MDIX Enable: Use a 2kΩ pull-down
resistor to disable. Leave open to enable.
90 IO_VDD Power I/O VDD: (Digital) Connect to 2.5V or 3.3V. The
VDD_SEL pin must be tied accordingly.
91 VSS Ground Ground: Connect to common ground plane.
92 CORE_VDD Power Core VDD: (Digital) Connect to 1.8V.
93 VSS Ground Ground: Connect to common ground plane.
94 MULTI_EN_STRAP Strap Multiple Node Enable: Use a 2kΩ pull-up resis-
tor to enable. Leave open to disable.
95 PHYADDR4_STRAP Strap PHY Address 4: See section
“5.9 LED/Strapping Option” on page 67 on how
to connect this pin.
96 AFE_VDD Power AFE VDD: (Analog) Connect to 2.5V.
97 VSS Ground Ground: Connect to common ground plane.
98 PGM_VDD Power PGM VDD: Connect to 1.8V through a low pass
filter. See section “5.4 Sensitive Supply Pins” on
page 64 for details.
99 VSS Ground Ground: Connect to common ground plane.
100 1V8_AVDD3 Power Analog Supply: Connect to 1.8V through a low
pass filter. See section “5.4 Sensitive Supply
Pins” on page 64 for details.
101 BG_VDD Power BG VDD: (Analog) Connect to 2.5V.
102 BG_REF Input BG Reference: See section “5.4 Sensitive Sup-
ply Pins” on page 64 on how to connect this pin.
103 RX_VDD Power Receive VDD: (Analog) Connect to 1.8V.
104 VSS Ground Ground: Connect to common ground plane.
105 RX_VDD Power Receive VDD: (Analog) Connect to 1.8V.
106 VSS Ground Ground: Connect to common ground plane.
Table 1.
Pin # Data Sheet Pin Name Type Connection / Comment