Datasheet

15 www.national.com
DP83865
1.0 Pin Description (Continued)
57 RX_CLK Output Receive Clock/ Receive Byte Clock 1: Con-
nect to MAC chip through a single 50 Ω imped-
ance trace. This output is capable of driving 35
pf load and is not intended to drive connectors,
cables, backplanes or multiple traces. This ap-
plies if the part is in 100 Mbps mode or 1000
Mbps mode.
58 IO_VDD Power I/O VDD: (Digital) Connect to 2.5V or 3.3V. The
VDD_SEL pin must be tied accordingly.
59 VSS Ground Ground: Connect to common ground plane.
60 TX_CLK/RGMII_SEL1 Output Transmit Clock: Connect to MAC chip through
a single 50 Ω impedance trace. This input has a
typical input capacitance of 6 pF.
61 TX_ER Input Transmit Error: Connect to MAC chip through a
single 50 Ω impedance trace. This input has a
typical input capacitance of 6 pF.
62 TX_EN/TXEN_ER Input Transmit Enable: Connect to MAC chip through
a single 50 Ω impedance trace. This input has a
typical input capacitance of 6 pF.
63 CORE_VDD Power Core VDD: (Digital) Connect to 1.8V.
64 VSS Ground Ground: Connect to common ground plane.
65 TXD7 Input Transmit Data 7: Connect to MAC chip through
a single 50 Ω impedance trace. This input has a
typical input capacitance of 6 pF.
66 TXD6 Input Transmit Data 6: Connect to MAC chip through
a single 50 Ω impedance trace. This input has a
typical input capacitance of 6 pF
67 TXD5 Input Transmit Data 5: Connect to MAC chip through
a single 50 Ω impedance trace. This input has a
typical input capacitance of 6 pF
68 TXD4 Input Transmit Data 4: Connect to MAC chip through
a single 50 Ω impedance trace. This input has a
typical input capacitance of 6 pF
69 IO_VDD Power I/O VDD: (Digital) Connect to 2.5V or 3.3V. The
VDD_SEL pin must be tied accordingly.
70 VSS Ground Ground: Connect to common ground plane.
71 TXD3/TX3 Input Transmit Data 3: Connect to MAC chip through
a single 50 Ω impedance trace. This input has a
typical input capacitance of 6 pF
72 TXD2/TX2 Input Transmit Data 2: Connect to MAC chip through
a single 50 Ω impedance trace. This input has a
typical input capacitance of 6 pF
73 CORE_VDD Power Core VDD: (Digital) Connect to 1.8V.
74 VSS Ground Ground: Connect to common ground plane.
75 TXD1/TX1 Input Transmit Data 1: Connect to MAC chip through
a single 50 Ω impedance trace. This input has a
typical input capacitance of 6 pF
76 TXD0/TX0 Input Transmit Data 0: Connect to MAC chip through
a single 50 Ω impedance trace. This input has a
typical input capacitance of 6 pF
77 IO_VDD Power I/O VDD: (Digital) Connect to 2.5V or 3.3V. The
VDD_SEL pin must be tied accordingly.
78 VSS Ground Ground: Connect to common ground plane.
Table 1.
Pin # Data Sheet Pin Name Type Connection / Comment