Datasheet

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DP83865
1.0 Pin Description (Continued)
23 RESERVED Reserved Reserved: Leave floating.
24 TCK Input JTAG Test Clock: This pin should be left float-
ing if not used.
25 CORE_VDD Power Core VDD: (Digital) Connect to 1.8V.
26 VSS Ground Ground: Connect to common ground plane.
27 TMS Input JTAG Test Mode Select: This pin should be left
floating if not used.
28 TDO Output JTAG Test Data Output: This pin should be left
floating if not used.
29 IO_VDD Power I/O VDD: (Digital) Connect to 2.5V or 3.3V. The
VDD_SEL pin must be tied accordingly.
30 VSS Ground Ground: Connect to common ground plane.
31 TDI Input JTAG Test Data Input: This pin should be left
floating if not used.
32 TRST
Input JTAG Test Reset: This pin should be pulled
down through a 2kΩ resistor if not used.
33 RESET
Input Reset: Connect to board reset signal.
34 VDD_SEL_STRAP Strap I/O VDD Select: Pull high to select 3.3V or low
to select 2.5V. The pin must be connected direct-
ly to power or ground (no pull-up/down resistor!).
35 CORE_VDD Power Core VDD: (Digital) Connect to 1.8V.
36 VSS Ground Ground: Connect to common ground plane.
37 IO_VDD Power I/O VDD: (Digital) Connect to 2.5V or 3.3V. The
VDD_SEL pin must be tied accordingly.
38 VSS Ground Ground: Connect to common ground plane.
39 COL Output Collision: Connect to MAC chip through a single
50 Ω impedance trace. This output is capable of
driving 35 pF load and is not intended to drive
connectors, cables, backplanes or multiple trac-
es. This applies if the part is in 100 Mbps mode
or 1000 Mbps mode.
40 CRS/RGMII_SEL0 Output Carrier Sense: Connect to MAC chip through a
single 50Ω impedance trace. This output is ca-
pable of driving 35 pf load and is not intended to
drive connectors, cables, backplanes or multiple
traces. This applies if the part is in 100 Mbps
mode or 1000 Mbps mode.
41 RX_ER/RXDV_ER Output Receive Error: Connect to MAC chip through a
single 50 Ω impedance trace. This output is ca-
pable of driving 35 pf load and is not intended to
drive connectors, cables, backplanes or multiple
traces. This applies if the part is in 100 Mbps
mode or 1000 Mbps mode.
42 IO_VDD Power I/O VDD: (Digital) Connect to 2.5V or 3.3V. The
VDD_SEL pin must be tied accordingly.
43 VSS Ground Ground: Connect to common ground plane.
44 RX_DV/RCK Output Receive Data Valid: Connect to MAC chip
through a single 50 Ω impedance trace. This out-
put is capable of driving 35 pf load and is not in-
tended to drive connectors, cables, backplanes
or multiple traces. This applies if the part is in
100 Mbps mode or 1000 Mbps mode.
Table 1.
Pin # Data Sheet Pin Name Type Connection / Comment