DP83865 DP83865 Gig PHYTER V 10/100/1000 Ethernet Physical Layer Literature Number: SNLS165B
DP83865 Gig PHYTER® V 10/100/1000 Ethernet Physical Layer General Description The DP83865 is a fully featured Physical Layer transceiver with integrated PMD sublayers to support 10BASE-T, 100BASE-TX and 1000BASE-T Ethernet protocols. The DP83865 is an ultra low power version of the DP83861 and DP83891. It uses advanced 0.18 um, 1.8 V CMOS technology, fabricated at National Semiconductor’s South Portland, Maine facility. The DP83865 is designed for easy implementation of 10/100/1000 Mb/s Ethernet LANs.
COMBINED MII / GMII / RGMII INTERFACE GTX_CLK TX_ER TX_EN TXD[7:0] TX_CLK RX_CLK COL CRS RX_ER RX_DV RXD[7:0] MGMT INTERFACE MDIO MDC Interrupt DP83865 Block Diagram µC MGMT & PHY CNTRL MUX/DMUX MII 10BASE-T Block 100BASE-TX Block MII MII 100BASE-TX PCS 10BASE-T PLS 100BASE-TX PMA 10BASE-T PMA 100BASE-TX PMD GMII 1000BASE-T Block GMII 1000BASE-T PCS Echo cancellation Crosstalk cancellation ADC Decode/Descramble Equalization Timing Skew compensation BLW 1000BASE-T PMA Manchester 10 Mb/s
Table of Contents 1.0 2.0 3.0 4.0 5.0 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 MAC Interfaces (MII, GMII, and RGMII) . . . . . . . 5 1.2 Management Interface . . . . . . . . . . . . . . . . . . . .7 1.3 Media Dependent Interface . . . . . . . . . . . . . . . .7 1.4 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.5 Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . .8 1.6 Device Configuration and LED Interface . . . . . .
DP83865 PQFP Pin Layout VSS MDID_N MDID_P VSS VSS 1V8_AVDD1 VSS MDIC_N MDIC_P VSS VSS 1V8_AVDD1 VSS MDIB_N MDIB_P VSS VSS 1V8_AVDD1 VSS MDIA_N MDIA_P VSS VSS 1V8_AVDD1 VSS 1V8_AVDD1 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 NON_IEEE_STRAP 1 102 BG_REF RESERVED 2 101 2V5_AVDD1 INTERRUPT 3 100 1V8_AVDD3 IO_VDD 4 99 VSS VSS 5 98 1V8_AVDD2 TX_TCLK / MAN_MDIX_STRAP 6 97 VSS
DP83865 1.
DP83865 1.0 Pin Description (Continued) Signal Name TXD0/TX0 Type PQFP Pin # I 76 TXD1/TX1 75 TXD2/TX2 72 TXD3/TX3 71 TXD4 68 TXD5 67 TXD6 66 TXD7 65 TX_EN/TXEN_ER I 62 Description TRANSMIT DATA: These signals carry 4B data nibbles (TXD[3:0]) during 10 Mbps and 100 Mbps MII mode, 4-bit data (TX[3:0]) in RGMII mode, and 8-bit data (TXD[7:0]) in 1000 Mbps GMII mode. They are synchronous to the transmit clocks (TX_CLK, TCK, GTX_CLK). Transmit data is input to PHY.
DP83865 1.0 Pin Description (Continued) 1.2 Management Interface Type PQFP Pin # MDC I 81 MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO serial management input/output data. This clock may be asynchronous to the MAC transmit and receive clocks. The maximum clock rate is 2.5 MHz and no minimum. MDIO I/O 80 MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may be sourced by the management station or the PHY. This pin requires a 2kΩ pullup resistor.
DP83865 1.0 Pin Description (Continued) Signal Name TCK Type PQFP PIn # I 24 Description TEST CLOCK: IEEE 1149.1 Test Clock input, primary clock source for all test logic input and output controlled by the testing entity. This pin should be left floating if not used. 1.5 Clock Interface Type PQFP Pin # CLK_IN I 86 CLOCK INPUT: 25 MHz oscillator or crystal input (50 ppm). CLK_OUT O 87 CLOCK OUTPUT: Second terminal for 25 MHz crystal. Must be left floating if a clock oscillator is used.
DP83865 1.0 Pin Description (Continued) Signal Name ACTIVITY_LED / SPEED0_STRAP Type I/O, S, PD PQFP Pin # 7 Description SPEED SELECT STRAP: These strap option pins have 2 different functions depending on whether Auto-Negotiation is enabled or not.
DP83865 1.0 Pin Description (Continued) Signal Name Type PQFP Pin # Description DUPLEX_LED / PHYADDR0_STRAP I/O, S, PU 13 PHYADDR1_STRAP PD 14 PHYADDR2_STRAP PD 17 PHYADDR3_STRAP PD 18 PD 95 DUPLEX STATUS: The LED is lit when the PHY is in Full Duplex operation after the link is established. I/O, S, PD 94 MULTIPLE NODE ENABLE: This pin determines if the PHY advertises Master (multiple nodes) or Slave (single node) priority during 1000BASE-T Auto-Negotiation.
DP83865 1.0 Pin Description (Continued) 1.8 Power and Ground Pins (See section “5.3 Power Supply Decoupling” on page 64.) Signal Name PQFP Pin # Description IO_VDD 4, 15, 21, 29, 37, 42, 53, 58, 69, 77, 83, 90 2.5V or 3.3V I/O Supply for “MAC Interfaces”, “Management Interface”, “JTAG Interface”, “Clock Interface”, “Device Configuration and LED Interface” and “Reset”. CORE_VDD 11, 19, 25, 35, 48, 63, 73, 92 1.8V Digital Core Supply 2V5_AVDD1 101 2.5V Analog Supply 2V5_AVDD2 96 2.
DP83865 1.0 Pin Description (Continued) 1.10 Pin Assignments in the Pin Number Order Table 1. Pin # Data Sheet Pin Name Type Connection / Comment Strap Non IEEE Compliant Mode Enable: Use a 2kΩ pull-up resistor to enable. Leave open to disable. 1 NON_IEEE_STRAP 2 RESERVED 3 INTERRUPT Output INTERRUPT: Connect to MAC or management IC. This is a tri-state pin and requires an external 2kΩ pull-up resistor if the pin is used. 4 IO_VDD Power I/O VDD: (Digital) Connect to 2.5V or 3.3V.
DP83865 1.0 Pin Description (Continued) Table 1. Pin # Data Sheet Pin Name Type Connection / Comment 23 RESERVED Reserved Reserved: Leave floating. 24 TCK 25 CORE_VDD Power Ground Ground: Connect to common ground plane. Input JTAG Test Clock: This pin should be left floating if not used. Core VDD: (Digital) Connect to 1.8V. 26 VSS 27 TMS Input JTAG Test Mode Select: This pin should be left floating if not used.
DP83865 1.0 Pin Description (Continued) Table 1. Pin # Data Sheet Pin Name Type Connection / Comment 45 RXD7 Output Receive Data 7: Connect to MAC chip through a single 50 Ω impedance trace. This output is capable of driving 35 pf load and is not intended to drive connectors, cables, backplanes or multiple traces. This applies if the part is in 100 Mbps mode or 1000 Mbps mode. 46 RXD6 Output Receive Data 6: Connect to MAC chip through a single 50 Ω impedance trace.
DP83865 1.0 Pin Description (Continued) Table 1. Pin # Data Sheet Pin Name Type Connection / Comment 57 RX_CLK Output Receive Clock/ Receive Byte Clock 1: Connect to MAC chip through a single 50 Ω impedance trace. This output is capable of driving 35 pf load and is not intended to drive connectors, cables, backplanes or multiple traces. This applies if the part is in 100 Mbps mode or 1000 Mbps mode. 58 IO_VDD Power I/O VDD: (Digital) Connect to 2.5V or 3.3V.
DP83865 1.0 Pin Description (Continued) Table 1. Pin # Data Sheet Pin Name Type Connection / Comment Input GMII Transmit Clock: Connect to MAC chip through a single 50 Ω impedance trace. This input has a typical input capacitance of 6 pF 79 GTX_CLK/TCK 80 MDIO Input / Output Management Data I/O: This pin requires a 2kΩ parallel termination resistor (pull-up to VDD). 81 MDC Input Management Data Clock: Connect to MAC or controller using a 50 Ω impedance trace.
DP83865 1.0 Pin Description (Continued) Table 1. Pin # Data Sheet Pin Name Type Connection / Comment 107 VSS Ground Ground: Connect to common ground plane. 108 MDIA_P Input / Output MDI Channel A Positive: Connect to TD+ of channel A of the magnetics. 109 MDIA_N Input / Output MDI Channel A Negative: Connect to TD- of channel A of the magnetics. 110 VSS Ground Ground: Connect to common ground plane. 111 RX_VDD Power 112 VSS Ground Ground: Connect to common ground plane.
DP83865 2.0 Register Block 2.1 Register Definitions Register maps and address definitions are given in the following table: Table 2.
19 0 ACK2 0 ACK2 0 Reserved 0 Reserved 0 Reserved 1 OUI[22] 0 OUI[6] 10BASE-T Full-Duplex 1 Register 0x0F (15’d) 1000BASE-T Extended Status Register (1KSCR) Register 0x0E (14’d) Reserved Register 0x0D (13’d) Reserved Register 0x0C (12’d) Reserved Register 0x0B (11’d) Reserved 1000BASE-X Half-Duplex 0 0 1000BASE-X Full-Duplex 0 0 0 Reserved Reserved 0 0 Reserved 0 Reserved Reserved 0 0 Reserved Reserved Reserved 1000BASE-T Full-Duplex 1 0 Reserved 0 Reserved 0 Rese
www.national.com TP_POL[2] 0 0 20 0, SC 0, SC 0 0, SC Clear Int. 0, SC Clear Int. 0 Reserved 0 Mask Int. Polarity Change Int. 0 100BASE-TX Link LED[1] 0 Reserved (RGMII Inband Sig. Enable) 0 Reserved (Power Down Status) 0 10 0, SC Clear Int. 0 Reserved 0 Mask Int. PDF Detection Fault Int. 0 100BASE-TX Link LED[0] 0 Reserved (RGMII Inband Sig.
DP83865 2.0 Register Block (Continued) 2.
DP83865 2.0 Register Block (Continued) Table 3. Basic Mode Control Register (BMCR) address 0x00 Bit Bit Name Default 11 Power_Down 0, RW Description Power Down: 1 = Power down (only Management Interface and logic active.) 0 = Normal operation. Note: This mode is internally the same as isolate mode (bit 10). 10 Isolate 0, RW Isolate: 1 = Isolates the Port from the MII/GMII with the exception of the serial management.
DP83865 2.0 Register Block (Continued) Table 4. Basic Mode Status Register (BMSR) address 0x01 12 10BASE-T Full Duplex 1, P 11 10BASE-T Half Duplex 1, P 100BASE-T2 Full Duplex 0, P 10 10BASE-T Full Duplex Capable: 1 = Device able to perform 10BASE-T in Full Duplex mode. 10BASE-T Half Duplex Capable: 1 = Device able to perform 10BASE-T in Half Duplex mode. 100BASE-T2 Full Duplex Capable: 0 = Device unable to perform 100BASE-T2 Full Duplex mode.
DP83865 2.0 Register Block (Continued) Table 5. PHY Identifier Register #1 (PHYIDR1) address 0x02 Bit Bit Name 15:0 OUI[3:18] Default Description 16’b<0010_0000 OUI Bits 3:18: _0000_0000>, P Bits 3 to 18 of the OUI (0x080017h) are stored in bits 15 to 0 of this register. The most significant two bits of the OUI are ignored (the IEEE standard refers to these as bits 1 and 2). The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83865.
DP83865 2.0 Register Block (Continued) Table 7. Auto-Negotiation Advertisement Register (ANAR) address 0x04 Bit Bit Name 8 100BASE-TX Full Duplex Default Description STRAP[1], RW 100BASE-TX Full Duplex Support: 1 = 100BASE-TX Full Duplex is supported by the local device. 0 = 100BASE-TX Full Duplex not supported. The default value of this bit is determined by the combination of the Duplex Enable and Speed[1:0] strap pins during reset/poweron IF Auto-Negotiation is enabled.
DP83865 2.0 Register Block (Continued) Table 8. Auto-Negotiation Link Partner Ability Register (ANLPAR) address 0x05 Bit Bit Name Default 15 NP 0, RO Description Next Page Indication: 0 = Link Partner does not desire Next Page Transfer. 1 = Link Partner desires Next Page Transfer. 14 ACK 0, RO Acknowledge: 1 = Link Partner acknowledges reception of the ability data word. 0 = Not acknowledged.
DP83865 2.0 Register Block (Continued) Table 9. Auto-Negotiate Expansion Register (ANER) address 0x06 Bit Bit Name Default 15:5 Reserved 0, RO 4 PDF 0, RO, LH Description Reserved by IEEE: Writes ignored, Read as 0. Parallel Detection Fault: 1 = A fault has been detected via the Parallel Detection function. 0 = A fault has not been detected via the Parallel Detection function. 3 LP_NP Able 0, RO Link Partner Next Page Able: 1 = Link Partner does support Next Page.
DP83865 2.0 Register Block (Continued) Table 10. Auto-Negotiation Next Page Transmit Register (ANNPTR) address 0x07 Bit Bit Name Default 11 TOG_TX 0, RO Description Toggle: 1 = Value of toggle bit in previously transmitted Link Code Word was logic 0. 0 = Value of toggle bit in previously transmitted Link Code Word was logic 1. Toggle is used by the Arbitration function within Auto-Negotiation to ensure synchronization with the Link Partner during Next Page exchange.
DP83865 2.0 Register Block (Continued) Table 11. Auto-Negotiation Next Page Receive Register (ANNPRR) address 0x08 Bit Bit Name Default 11 TOG_RX 0, RO Description Toggle: 1 = Value of toggle bit in previously transmitted Link Code Word was logic 0. 0 = Value of toggle bit in previously transmitted Link Code Word was logic 1. Toggle is used by the Arbitration function within Auto-Negotiation to ensure synchronization with the Link Partner during Next Page exchange.
DP83865 2.0 Register Block (Continued) Table 12. 1000BASE-T Control Register (1KTCR) address 0x09 Bit Bit Name 9 1000BASE-T Full Duplex Default Description STRAP[1], RW Advertise 1000BASE-T Full Duplex Capable: 1 = Advertise DTE as 1000BASE-T Full Duplex Capable. 0 = Advertise DTE as not 1000BASE-T Full Duplex Capable. (The default value of this bit is determined by the combination of the Duplex Enable and Speed[1:0] strap pins during reset/poweron IF Auto-Negotiation is enabled.
DP83865 2.0 Register Block (Continued) Table 14. 1000BASE-T Extended Status Register (1KSCR) address 0x0F (15’d) Bit Bit Name Default 15 1000BASE-X Full Duplex 0, P Description 1000BASE-X Full Duplex Support: 1 = 1000BASE-X is supported by the local device. 0 = 1000BASE-X is not supported. DP83865 does not support 1000BASE-X and bit should always be read back as “0”. 14 1000BASE-X Half Duplex 0, P 1000BASE-X Half Duplex Support: 1 = 1000BASE-X is supported by the local device.
DP83865 2.0 Register Block (Continued) Table 16. Link and Auto-Negotiation Status Register (LINK_AN) address 0x11 (17’d) Bit Bit Name Default Description 15:12 TP Polarity[3:0] 0, RO Twisted Pair Polarity Status: Indicates a polaritiy reversal on pairs A to D ([15:12]). The PHY automatically detects this condition and adjusts for it. 1 = polarity reversed 0 = normal operation 11 Reserved 0, RO (Power Down Status) 10 MDIX Status Write as 0, ignore on read.
DP83865 2.0 Register Block (Continued) Table 17. Auxiliary Control Register (AUX_CTRL) address 0x12 (18’d) Bit Bit Name 15 Auto-MDIX Enable Default Description STRAP[1], RW Automatic MDIX: Indicates (sets) whether the PHY’s capability to automatically detect swapped cable pairs is used. 1 = Automatic MDIX mode, bit 14 is ignored 0 = Manual MDIX mode Note: This bit is ignored and the setting of bit 14 applies if AutoNegotiation is disabled (AN_EN = 0).
DP83865 2.0 Register Block (Continued) Table 17. Auxiliary Control Register (AUX_CTRL) address 0x12 (18’d) Bit Bit Name Default Description 5 Shallow Deep Loopback Enable 0, RW Shallow Deep Loopack Enable: (Loopback status bit 7, register 0x11) This bit places PHY in the MAC side loopback mode. Any packet entering into TX side appears on the RX pins immediately. This operation bypasses all internal logic and packet does not appear on the MDI interface.
DP83865 2.0 Register Block (Continued) Table 18. LED Control Register (LED_CTRL) address 0x13 (19’d) Bit Bit Name Default Description 5 reduced LED enable 0, RW Reduced LED Mode Enable: This bit enables the reduced LED (RLED) mode that is different from the normal five-LED mode. In the RLED Mode, 10M Link LED is changed to link LED or Link and activity combined LED. When reg 0x13.5 is enabled: Reg 0x1A.0 = 1 - 10M Link LED displays 10/100/1000 Link Reg 0x1A.
DP83865 2.0 Register Block (Continued) Table 20. Interrupt Mask Register (INT_MASK) address 0x15 (21’d) Bit Bit Name Default Description 15 spd_cng_int_msk 0, RW Setting this bit activates the spd_cng_int interrupt. The interrupt is masked if the bit is cleared. 14 lnk_cng_int_msk 0, RW Setting this bit activates the lnk_cng_int interrupt. The interrupt is masked if the bit is cleared. 13 dplx_cng_int_msk 0, RW Setting this bit activates the dplx_cng_int interrupt.
DP83865 2.0 Register Block (Continued) Table 22. Interrupt Clear Register (INT_CLEAR) address 0x17 (23’d) Bit Bit Name Default Description 15 spd_cng_int_clr 0, RW, SC Setting this bit clears the spd_cng_int interrupt. 14 lnk_cng_int_clr 0, RW, SC Setting this bit clears the lnk_cng_int interrupt. 13 dplx_cng_int_clr 0, RW, SC Setting this bit clears the dplx_cng_int interrupt. 12 mdix_cng_int_clr 0, RW, SC Setting this bit clears the mdix_cng_int interrupt.
DP83865 2.0 Register Block (Continued) Table 24. BIST Configuration Register 1 (BIST_CFG1) address 0x19 (25’d) Bit Bit Name Default 10 tx_bist_pak_type 0, RW Description Transmit BIST Packet Type: 1 = PSR9 0 = User defined packet 9:8 Reserved 0, RO Write as 0, ignore on read. 7:0 tx_bist_pak 0, RW User Defined Packet Content: This field sets the packet content for the transmit BIST packets if the user defined packet type in bit 10 is selected. Table 25.
DP83865 2.0 Register Block (Continued) Table 28. PHY Support Register #2 (PHY_SUP) address 0x1F (31’d) Bit Bit Name Default 15:5 Reserved 0, RO 4:0 PHY Address Description Write as 0, ignore on read. STRAP[0_0001], PHY Address: Defines the port on which the PHY will accept SeRW rial Management accesses. 39 www.national.
DP83865 3.0 Configuration This section includes information on the various configuration options available with the DP83865. The configuration options include: There are three registers used for accessing the expanded memory. The Expanded Memory Access Control resiger (0x16) sets up the memory access mode, for example, 8bit or 16-bit data addess, enable or disable automatic address increment after each access, and read/write or write-only opeation.
DP83865 3.0 Configuration (Continued) . Table 29. Speed/Duplex Selection, AN_EN = 0 DUPLEX SPEED[1] SPEED[0] Manual Mode 0 0 0 10BASE-T HD 0 0 1 100BASE-TX HD 0 1 0 1000BASE-T HD (Between National PHYs only) 0 1 1 Reserved 1 0 0 10BASE-T FD 1 0 1 100BASE-TX FD 1 1 0 1000BASE-T FD (Between National PHYs only) 1 1 1 Table 31. Master/Slave Resolution, AN_EN = 0 Reserved 3.2.
DP83865 3.0 Configuration (Continued) The default for AN Speed Fallback is that after five tries to achieve a stable link, the link speed will drop down to the next lower advertised speed. The default CRC and IE Speed Fallback is that after five link drops due to increase error rate, the link speed drops down to the next lower advertised speed.
resolved by a random number generation. See IEEE 802.3ab Clause 40.5.1.2 for more details. ANNPTR 0x07 allows for the configuration and transmission of the Next Page. Refer to clause 28 of the IEEE 802.3u standard for detailed information regarding the Auto-Negotiation Next Page function. Table 36. 1000BASE-T Single/Multi-Node, AN_EN = 1 MULTI_EN 3.3.
DP83865 3.0 Configuration (Continued) 3.4 Auto-Negotiation Register Set During the next page exchange operation, the station manager can not wait till the end of Auto-Negotiation to read the ANLPAR because the register is used to store both the base and next pages. The next page content overwrites the base page content. The station manager needs to closely monitor the negotiation status and to perform the following tasks.
To enable Auto-MDIX, strapping option pin MDIX_EN should be pulled up or left floating. Auto-MDIX can be disabled by strapping MDIX_EN pin low. When Auto-MDIX is disabled, the PMA is forced to either MDI (“straight”) or MDIX (“crossed”) - according to the setting of the MAN_MDIX strapping option pin (high for MDIX and low for MDI). and it is implemented on DP83865DVH. Note that the reduced LED mode is in addition to the existing five-LED mode.
DP83865 3.0 Configuration (Continued) 3.10.1 MII/GMII Interface Note that upon power up, the clock output is available after GPHY goes through its internal reset and initialization process. The clock output can be interrupted when GPHY is going through software reset. The link speed is determined by Auto-Negotiation, by strapping options, or by register writes. Based on the speed linked, an appropriate MAC interface is enabled. 3.
See IEEE 802.3ab section 40.6.1.1.2 “Test modes” for more information on the nature of the test modes. BIST. The receive BIST contains a receive error counter and receive packet counter and the transmit BIST is used to generate Ethernet packets. The DP83865 provides a test clock synchronous to the IEEE test patterns. The test patterns are output on the MDI pins of the device and the test clock is output on the TX_TCLK pin.
DP83865 3.0 Configuration (Continued) 3.20 10BASE-T Half Duplex Loopback During transmit BIST operation the transmit path (TXD[7:0]) of the GMII / MII is disabled. All generated packets will be sent out to the MDI path unless the loopback mode is enabled. In that case the generated packets will be presented at the receive path (RXD[7:0]) of the GMII / MII. By default, the 10BASE-T half duplex transmitted packets are looped back to the receive side. This is a legacy implementation.
The DP83865 is a full featured 10/100/1000 Ethernet Physical layer (PHY) chip. It consists of a digital 10/100/1000 Mb/s core with a common TP interface. It also has a combined versitle MAC interface that is capable of interfacing with MII and GMII controller interfaces. In this section, the following topics are covered: — — — — — — — — — 4.1.2 Data and Symbol Sign Scrambler Word Generator The word generator uses the Scrn[32:0] to generate further scrambled values.
DP83865 4.
DP83865 4.0 Functional Description (Continued) PARTIAL RESPONSE PULSE SHAPE CODING 5-LEVEL PAM-5 TO 17-LEVEL PAM SIGN SCRAMBLER PAM-5 3-bits/sample Z -1 0.75 0.25 17-LEVEL PAM-5 5-bits/sample TABLE LOOKUP DAC CONTROL 20-bits/sample MUX 0.75∗X(k) + 0.25∗X(k-1) 10 100 1000 DAC Manchester/ MLT-3/PAM-17 ANALOG 2-bit MLT-3 Manchester coding PMA Transmitter Block Figure 3. PMA Transmitter Block PAM-5 w ith PR (.7 5+.2 5T) Transmit Spectra PAM-5 1.200 Re lativ e Amp litud e 1.000 0.800 0.
DP83865 4.0 Functional Description (Continued) 4.4.5 Receive State Machine 1000BASE-T transceiver and shows the functionality of the PCS receiver. The state machine operation is defined in IEEE 802.3ab section 40.3.1.4. In summary, it provides the necessary receive control signals of RX_DV and RX_ER to the GMII. In specific conditions defined in the IEEE 802.3ab specification, it generates RXD[7:0] data.
DP83865 4.0 Functional Description (Continued) The mapping of the MAC interface is illustrated below in Table 51. RGMII Table 51. GMII/RGMII/MII Mapping GMII RGMII MII RXD[3:0] RX[3:0] RXD[3:0] TX_CLK TD0 TD1 TD2 RXD[4:7] RX_DV RCK RX_ER RXDV_ER RX_CLK TXD[3:0] TD3 TXEN_ER RX_DV RX_ER TX_CLK TX[3:0] TXD[3:0] RD0 TXEN_ER TX_EN RD1 RD2 RD3 RXDV_ER TXD[4:7] TX_EN TX_ER GTX_CLK TX_ER Figure 5.
DP83865 4.0 Functional Description (Continued) 1000 Mbps Mode Transmit Path Timing serial data stream for 100BASE-TX operation. Since the 10BASE-T and 100BASE-TX transmitters are integrated with the 1000BASE-T, the differential output pins, TD+ /are routed to channel A of the AC coupling magnetics. In the transmit path, the TX signals are the output of the MAC and input of the PHY. The MAC output has a data to clock skew of -500 ps to +500 ps in both HP and 3COM mode.
DP83865 4.0 Functional Description (Continued) TX_CLK 100BASE-T 10BASE-T TXD[3:0] / TX_ER TXD[3:0] / TX_ER 4B/5B ENCODER AND INJECTION LOGIC NRZ TO MANCHESTER DECODER DIVIDER FROM PGM LINK PULSE GENERATOR PARALLEL TO SERIAL SCRAMBLER NRZ-TO-NRZI 100BASE-X LOOPBACK BINARY-TO-MLT 10, 100, 1000 MUX/DAC/DRIVER MDI +/− Figure 6. 10BASE-T/100BASE-TX Transmit Block Diagram 4.7.5 100BASE-T Code-group Encoding and Injection 4.7.
DP83865 4.0 Functional Description (Continued) dB. The DP83865 uses the PHYADDR[4:0] value to set a unique seed value for the scramblers. The resulting energy generated by each channel is out of phase with respect to each channel, thus reducing the overall electro-magnetic radiation. Table 52. 4B5B Code-Group Encoding/Decoding Name 4.7.
4.7.9 MLT-3 Converter / DAC / Line Driver phased logic one events. These two binary streams are then passed to a 10/100/1000 DAC and line driver which converts the pulses to suitable analog line voltages. Refer to Figure 8.
DP83865 4.0 Functional Description (Continued) 10BASE-T RXD[3:0] / RX_ER RX_CLK RXD[3:0] / RX_ER 100BASE-TX 5B/4B DECODER LOGIC 4-BIT NIBBLE DEMUX DIVIDER SERIAL TO PARALLEL MANCHESTER TO NRZ DECODER DESCRAMB LER MLT-3 TO NRZ CLOCK & DATA RECOVERY LINK DETECT CLOCK RECOVERY AAC BLW EQ CORRECTN SIGNAL DETECT LINK DETECT SIGNAL DETECT ADC RECEIVER 100BASE-TX 10BASE-T MDI +/− Figure 8. 10BASE-T/100BASE-T Receive Block Diagram after the last bit, carrier sense is de-asserted.
DP83865 4.0 Functional Description (Continued) Figure 9. 100BASE-TX BLW Event in potentially serious BLW. The digital oscilloscope plot provided in Figure 9 illustrates the severity of the BLW event that can theoretically be generated during 100BASE-TX packet transmission. This event consists of approximately 800 mV of DC offset for a period of 120 ms. Left uncompensated, events such as this can cause packet loss.
DP83865 4.0 Functional Description (Continued) The CRM is implemented using an advanced digital Phase Locked Loop (PLL) architecture that replaces sensitive analog circuitry. Using digital PLL circuitry allows the DP83865 to be manufactured and specified to tighter tolerances. version ceases upon the detection of the /T/R/ code-group pair denoting the End of Stream Delimiter (ESD) or with the reception of a minimum of two IDLE code-groups. 4.8.
— — — — — Serial Management Preample Suppression PHY Address Sensing MII Data Interface MII Isolate Mode Status LED’s order to initialize the MDIO interface, the station management entity sends a sequence of 32 contiguous logic ones on MDIO to provide the DP83865 with a sequence that can be used to establish synchronization.
DP83865 4.0 Functional Description (Continued) MDC MDIO Z Z (STA) Z Idle 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Start Opcode (Write) PHY Address (PHYAD = 0Ch) Register Address (00h = BMCR) TA Register Data Z Idle Figure 12. Typical MDC/MDIO Write Operation 4.9.4 PHY Address Sensing 4.9.7 Status Information The DP83865 provides five PHY address pins to set the PHY address. The information is latched into the STRAP_REG 0x10.4:0 at device power-up or reset.
5.1 Hardware Reset The design guide in conjunction with the Reference Design Schematics/BOM is intended to provide information to assist in the design and layout of the DP83865 Gigabit Ethernet Transceiver.
DP83865 5.0 Design Guide (Continued) between the ground and VDD plane also minimizes EMI radiation. introduce inductive coupling leading to ground bounce. Connect power and ground pins directly to the planes. Any through-hole clock oscillator component should be mounted as flat and as close to the PCB as possible. Excessive leads should be trimmed. Provide a ground pad equal or larger than the oscillator foot print on the component side of the PCB.
DP83865 5.0 Design Guide (Continued) VDD = 1.8 V DP83865 VDD = 1.8 V CORE_VDD 18 Ω 1V8_AVDD2 Low pass filter for 1V8_AVDD2 only 0.01 µF 0.1 µF 0.01 µF 22 µF GND GND 1V8_AVDD1 VDD = 2.5 V 0.01 µF IO_VDD GND 0.1 µF 0.01 µF Typical supply bypassing (Near pins of the device) VDD = 2.5 V GND 2V5_AVDD2 2V5_AVDD1 0.01 µF 9.76 kΩ 0.01 µF BG_REF GND 1% GND VDD = 1.8 V 10 Ω 1V8_AVDD3 Low pass filter for 1V8_AVDD3 only 22 µF GND Figure 15. Power Supply Filtering PHY 1.8 Digital section 2.
DP83865 5.0 Design Guide (Continued) Termination Requirement The purpose of the series termination is to reduce reflections and to improve the signal quality. The board designer should evaluate the reflection and signal integrity to determine the need for the termination in each design. As a general rule, if the trace length is less than 1/6 of the equivalent length of the rise and fall times, the series termination is not needed. The following is an example of calculating the signal trace length.
5.8 RJ-45 Connections — The EMI can be further reduced by placing the traces in the inner layers and making the outer layers chassis ground. — Generally, it is a good practice not to overlap the circuit ground plane with the chassis ground that creates coupling. Instead, make chassis ground an isolated island and make a void between the chassis and circuit ground. Place two or three 1206 pads across the chassis and circuit ground void.
DP83865 5.0 Design Guide (Continued) board space, the adjacent unused input pins can be grouped and tied together with a single resistor. typically 95% of its nominal voltage varies from design to design. The number of unused pins and which pins become unused pins highly depend on the individual application the DP83865 is used in. Refer to Section 1.0 for each individual pin that is not used. There is no specific requirement for power-up sequence for the DP83865.
DP83865 5.0 Design Guide (Continued) Table 56. Recommended Crystal Oscillators Manufacturer Description Part Number Vite Technology www.viteonline.com 25 MHz 7.5 x 5 mm Oscillator VCC1-B2B-25M000 Raltron www.raltron.com 25 MHz 7.5 x 5 mm Oscillator C04305L-25.000MHz Pericom www.saronix.com 25MHz Oscillator NCH089B3-25.0000 Abracon www.abracon.com 25MHz Oscillator ACSHL-25.0000-E-C-C4 Pletronics www.pletronics.com 25MHz Oscillator SQ2245V-25.
DP83865 5.0 Design Guide (Continued) 5.13.2 Magnetics It is important to select the compoment that meets the requirements. Per IEEE 802.3ab Clause 40.8, the component requirements are listed in Table 57. In addition, the transformer winding should have the configuration shown in Figure 21. The recommended magnetics has an isolation transformer followed by a common mode choke to reduce EMI. There is an additional auto-transformer which is center tapped.
DP83856 6.0 Electrical Specifications Absolute Maximum Ratings Recommended Operating Condition Min Typ Max Units Supply Voltage IO_VDD -0.4V to 4.2 V Supply Voltage CORE_VDD, 1V8_AVDD1, 1V8_AVDD2 -0.4V to 2.4V Supply Voltage IO_VDD 3.135 3.3 3.465 V V Supply Voltage 2V5_AVDD1, 2V5_AVDD2 -0.4V to 3.6V Supply Voltage IO_VDD 2.375 2.5 2.625 Analog Voltages 2V5_AVDD1, 2V5_AVDD2 Supply Voltage CORE_VDD Analog Voltages 1V8_AVDD1, 1V8_AVDD2 1.
DP83856 6.0 Electrical Specifications (Continued) Symbol Pin Types VIL non-R/GMII I I/O I/O_Z Input Low Voltage VOH non-R/GMII O, I/O I/O_Z Output High Voltage VOL non-R/GMII O, I/O I/O_Z Output Low Voltage R strap Strap PU/PD internal resistor value. CIN1 COUT1 R0 R/GMII VOD-10 VOD-100 VOD-1000 I O, I/O I/O_Z O, I/O_Z (MDI) (MDI) (MDI) Parameter Conditions IO_VDD = 2.5V IO_VDD = 3.3V Typ Max Units GND 0.8 V (IO_VDD 0.5) IO_VDD V GND 0.4 V IOH = -4.0 mA for both IOL = 4.
DP83856 6.0 Electrical Specifications (Continued) 6.2 Reset Timing VDD 1.8V (core, analog), 2.5V (I/O, analog), 3.3V (I/O if applicable) T1 CLK_IN T2 RESET 32 clocks T3 MDC T4 Latch-In of Hardware Configuration Pins T5 CLK_TO_MAC Parameter T1 Description Notes Min Typ Max Units Reference clock settle time The reference clock must be stable after the last power supply voltage has settled and before RESET is deasserted.
DP83856 6.0 Electrical Specifications (Continued) 6.3 Clock Timing T7 T7 CLK_IN T6 T8 Parameter Description T6 CLK_IN Duty Cycle T7 CLK_IN tR/tF T8 CLK_IN frequency (25 MHz +/-50 ppm) Notes Min Typ Max Units 60 % 40 10% to 90% 1.0 to 2.5 ns 24.99875 25.000000 25.001250 MHz 6.4 1000 Mb/s Timing 6.4.
DP83856 6.0 Electrical Specifications (Continued) 6.4.2 GMII Receive Timing T16 T17 T17 RX_CLK T15 RXD[7:0] RX_DV RX_ER Valid Data T18 MDI Begin of Frame Parameter Description T15 ↑ RX_CLK to RXD, RX_DV and RX_ER delay T16 RX_CLK Duty Cycle T17 RX_CLK tR/tF T18 Note 1: Note 2: Note 3: Note 4: Note 5: Notes Min Typ Max Note 2, 3, 4 0.5 5.5 40 60 % 1 ns Note 1, 4, 5 MDI to GMII latency 384 Units ns ns tr and tf are measured from VIL_AC(MAX) = 0.7V to VIH_AC(MIN) = 1.9V.
DP83856 6.0 Electrical Specifications (Continued) 6.5 RGMII Timing 6.5.1 Transmit and Receive Multiplexing and Timing TX [3:0] TXD[3:0] TXD[7:4] TXEN_ER TX_EN TX_ER TXD[3:0] TX_EN TXD[7:4] TX_ER TCK TskewT Tcyc RCK RX [3:0] RXDV_ER RXD[3:0] RXD[7:4] RX_DV RX_ER RXD[3:0] RXD[7:4] RX_DV RX_ER TholdR TskewR TsetupR Parameter Tcyc Description Notes Min Typ Max Units TskewT TX to Clock skew (at receiver, PHY), HP mode Note 1 1.0 2.
DP83856 6.0 Electrical Specifications (Continued) 6.6 100 Mb/s Timing 6.6.1 100 Mb/s MII Transmit Timing T21 T20 TX_CLK TXD[3:0], TX_EN, TX_ER T19 T22 MDI Begin of Frame Parameter Description Notes Min Typ Max Units T19 TXD[3:0], TX_EN and TX_ER Setup to ↑ TX_CLK 10 ns T20 TXD[3:0], TX_EN and TX_ER Hold from ↑ TX_CLK -1 ns T21 TX_CLK Duty Cycle 40 T22 MII to MDI latency 60 136 % ns 6.6.
DP83856 6.0 Electrical Specifications (Continued) 6.7 10 Mb/s Timing 6.7.1 10 Mb/s MII Transmit Timing T28 T27 TX_CLK TXD[3:0], TX_EN, TX_ER T26 T29 MDI Begin of Frame Parameter Description Notes T26 TXD[3:0], TX_EN and TX_ER Setup to ↑ TX_CLK T27 Min Typ Max Units 100 ns TXD[3:0], TX_EN and TX_ER Hold from ↑ TX_CLK 0 ns T28 TX_CLK Duty Cycle 40 T29 MII to MDI latency 60 125 % ns 6.7.
DP83856 6.0 Electrical Specifications (Continued) 6.8 Loopback Timing GTX_CLK TX_CLK TX_EN TXD[7:0] TXD[3:0] Valid Data CRS T33 RX_CLK RX_DV RXD[7:0] RXD[3:0] Parameter T33 Valid Data Description TX_EN to RX_DV Loopback Notes Min Typ 10 Mb/s 2220 100 Mb/s 380 1000 Mb/s 536 Max Units ns Note: During loopback (all modes) both the TD± outputs remain inactive by default. 79 www.national.
DP83856 6.0 Electrical Specifications (Continued) 6.9 Serial Management Interface Timing MDC T34 T35 MDIO (output) MDC T36 MDIO (input) Parameter T37 Valid Data Description Notes Min Typ Max Units 2.5 MHz 300 ns T34 MDC Frequency T35 MDC to MDIO (Output) Delay Time T36 MDIO (Input) to MDC Setup Time 10 ns T37 MDIO (Input) to MDC Hold Time 10 ns www.national.
DP83856 6.0 Electrical Specifications (Continued) 6.10 Power Consumption Symbol I1V8_1000 Pin Types Parameter Conditions 1V8_AVDD, 1V8 Core_VDD current Core_VDD = 1.8V, 1V8_AVDD = 1.8V, 2V5_AVDD current 2V5_AVDD = 2.5V, I2V5_IO_1000 IO_VDD current I3V3_IO_1000 IO_VDD current I2V5_1000 Min Typ Max Units 0.43 A 0.19 A IO_VDD = 2.5V, 1000 Mbps FDX 0.01 A IO_VDD = 3.3V, 0.01 A 0.07 A 0.
DP83856 7.0 Frequently Asked Questions 7.1 Do I need to access any MDIO register to start up the PHY? the internal 125 MHz clock generated from the CLOCK_IN clock to transmit data on the wire. The Slave PHY uses the clock recovered from the link partner’s transmission as the transmit clock for all four pairs. A: The answer is no. The PHY is a self contained device. The initial settings of the PHY are configured by the strapping option at the pins.
DP83856 7.0 Frequently Asked Questions (Continued) in advance what mode the link partner is operating, there could be conflict if both PHY are operating in Master or both in Slave mode. It is recommended that under normal operation, AN_EN is enabled. TC = TJ - Pd(Οc) Where: TJ = Junction temperature of the die in oC TC = Case temperature of the package in oC Pd = Power dissipated in the die in Watts Oc = 17oC/watt 7.
DP83856 7.0 Frequently Asked Questions (Continued) 7.18 What are some other applicable documents? A: For updated collateral material, please go to “solutions.national.com” website. — DP83865 Reference Design (Demo board, Schematics, BOM, Gerber files.
DP83865 NOTES www.national.
P83865 Gig PHYTER V 10/100/1000 Ethernet Physical Layer 8.0 Physical Dimensions inches (millimeters) unless otherwise noted 128 Lead Plastic Flat Pack LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.
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