Datasheet

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DP83849I
Figure 6. Typical MDC/MDIO Write Operation
3.6.3 Serial Management Preamble Suppression
The DP83849I supports a Preamble Suppression mode as
indicated by a one in bit 6 of the Basic Mode Status Regis
-
ter (BMSR, address 01h.) If the station management entity
(i.e. MAC or other management controller) determines that
all PHYs in the system support Preamble Suppression by
returning a one in this bit, then the station management
entity need not generate preamble for each management
transaction.
The DP83849I requires a single initialization sequence of
32 bits of preamble following hardware/software reset. This
requirement is generally met by the mandatory pull-up
resistor on MDIO in conjunction with a continuous MDC, or
the management access made to determine whether Pre
-
amble Suppression is supported.
While the DP83849I requires an initial preamble sequence
of 32 bits for management initialization, it does not require
a full 32-bit sequence between each subsequent transac-
tion. A minimum of one idle bit between management
transactions is required as specified in the IEEE 802.3u
specification.
3.6.4 Simultaneous Register Write
The DP83849I incorporates a mode which allows simulta-
neous write access to both Port A and B register blocks at
the same time. This mode is selected by setting bit 15 of
RMII and Bypass Register (RBR, address 17h) in Port A.
As long as this bit remains set, subsequent writes to Port A
will write to registers in both ports.
Register reads are unaffected. Each port must still be read
individually.
MDC
MDIO
00011110000000
(STA)
Idle Start
Opcode
(Write)
PHY Address
(PHYAD = 0Ch)
Register Address
(00h = BMCR)
TA
Register Data
Z
0 0 0 000 00000000
Z
Idle
1000
ZZ