Datasheet

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DP83849I
8.2.29 Single Clock MII (SCMII) Receive Timing
Note: Output delays assume a 25pF load.
Note: CRS is asserted and deasserted asynchronously relative to the reference clock.
Note: CRS ON delay is measured from the first bit of the JK symbol on the PMD Receive Pair to assertion of CRS_DV.
Note: CRS_OFF delay is measured from the first bit of the TR symbol on the PMD Receive Pair to deassertion of
CRS_DV.
Note: Receive Latency is measured from the first bit of the symbol pair on the PMD Receive Pair. Typical values are with
the Elasticity Buffer set to the default value (01).
Parameter Description Notes Min Typ Max Units
T2.29.1 X1 Clock Period 25MHz Reference Clock 40 ns
T2.29.2 RXD[3:0], RX_DV and RX_ER
output delay
From X1 rising 2 18 ns
T2.29.3 CRS ON delay (100Mb) 100BASE-TX mode 19 bits
T2.29.4 CRS OFF delay (100Mb) 100BASE-TX mode 26 bits
T2.29.5 RXD[1:0] and RX_ER latency
(100Mb)
100BASE-TX mode 56 bits
X1
CRS
RX_DV
T2.29.1
T2.29.2
PMD Input Pair
IDLE
Data
(J/K)
T2.29.3
T2.29.5
Data
(TR)
T2.29.4
RXD[1:0]
RX_ER
T2.29.2