Datasheet

DP83849IF
www.ti.com SNOSAX8D –JUNE 2009–REVISED APRIL 2013
3.3 SERIAL MANAGEMENT INTERFACE
Signal Name Type Pin # Description
MDC I 67 MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/output
serial interface which may be asynchronous to transmit and receive clocks. The maximum clock
rate is 25 MHz with no minimum clock rate.
MDIO I/O 66 MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may be
sourced by the station management entity or the PHY. This pin requires a 1.5 kΩ pullup resistor.
3.4 MAC DATA INTERFACE
Signal Name Type Pin # Description
TX_CLK_A O 12 MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100 Mb/s mode or 2.5 MHz in 10 Mb/s
TX_CLK_B 50 mode derived from the 25 MHz reference clock.
Unused in RMII mode. The device uses the X1 reference clock input as the 50 MHz reference for
both transmit and receive.
SNI TRANSMIT CLOCK: 10 MHz Transmit clock output in 10 Mb SNI mode. The MAC should
source TX_EN and TXD_0 using this clock.
TX_EN_A I 13 MII TRANSMIT ENABLE: Active high input indicates the presence of valid data inputs on
TX_EN_B 49 TXD[3:0].
RMII TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD[1:0].
SNI TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD_0.
TXD[3:0]_A I 17,16,15,14, MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0], that accept data synchronous to
TXD[3:0]_B 45,46,47,48 the TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode).
RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0], that accept data synchronous to
the 50 MHz reference clock.
SNI TRANSMIT DATA: Transmit data SNI input pin, TXD_0, that accept data synchronous to the
TX_CLK (10 MHz in 10 Mb/s SNI mode).
RX_CLK_A O 79 MII RECEIVE CLOCK: Provides the 25 MHz recovered receive clocks for 100 Mb/s mode and 2.5
RX_CLK_B 63 MHz for 10 Mb/s mode.
Unused in RMII mode. The device uses the X1 reference clock input as the 50 MHz reference for
both transmit and receive.
SNI RECEIVE CLOCK: Provides the 10 MHz recovered receive clocks for 10 Mb/s SNI mode.
RX_DV_A O 80 MII RECEIVE DATA VALID: Asserted high to indicate that valid data is present on the
RX_DV_B 62 corresponding RXD[3:0].
RMII RECEIVE DATA VALID: Asserted high to indicate that valid data is present on the
corresponding RXD[1:0]. This signal is not required in RMII mode, since CRS_DV includes the
RX_DV signal, but is provided to allow simpler recovery of the Receive data.
This pin is not used in SNI mode.
RX_ER_A O 2 MII RECEIVE ERROR: Asserted high synchronously to RX_CLK to indicate that an invalid symbol
RX_ER_B 60 has been detected within a received packet in 100 Mb/s mode.
RMII RECEIVE ERROR: Asserted high synchronously to X1 whenever an invalid symbol is
detected, and CRS_DV is asserted in 100 Mb/s mode. This pin is also asserted on detection of a
False Carrier event. This pin is not required to be used by a MAC in RMII mode, since the Phy is
required to corrupt data on a receive error.
This pin is not used in SNI mode.
RXD[3:0]_A O 9,8,5,4,53, MII RECEIVE DATA: Nibble wide receive data signals driven synchronously to the RX_CLK, 25
RXD[3:0]_B 56,57,58 MHz for 100 Mb/s mode, 2.5 MHz for 10 Mb/s mode). RXD[3:0] signals contain valid data when
RX_DV is asserted.
RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driven synchronously to the X1 clock,
50 MHz.
SNI RECEIVE DATA: Receive data signal, RXD_0, driven synchronously to the RX_CLK. RXD_0
contains valid data when CRS is asserted. RXD[3:1] are not used in this mode.
CRS_A/CRS_ O 1 MII CARRIER SENSE: Asserted high to indicate the receive medium is non-idle.
DV_A 61 RMII CARRIER SENSE/RECEIVE DATA VALID: This signal combines the RMII Carrier and
CRS_B/CRS_ Receive Data Valid indications. For a detailed description of this signal, see the RMII Specification.
DV_B SNI CARRIER SENSE: Asserted high to indicate the receive medium is non-idle. It is used to
frame valid receive data on the RXD_0 signal.
Copyright © 2009–2013, Texas Instruments Incorporated Pin Descriptions 9
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