Datasheet

DP83849IF

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SNOSAX8D –JUNE 2009–REVISED APRIL 2013

Table 10-19. RMII and Bypass Register (RBR), addresses 17h (continued)

Bit Bit Name Default Description

4 RMII_REV1_0 0, RW Reduced MII Revision 1.0:

0 = (RMII revision 1.2) CRS_DV will toggle at the end of a packet to indicate

deassertion of CRS.

1 = (RMII revision 1.0) CRS_DV will remain asserted until final data is transferred.

CRS_DV will not toggle at the end of a packet.

3 RX_OVF_STS 0, RO/COR RX FIFO Over Flow Status:

0 = Normal.

1 = Overflow detected.

2 RX_UNF_STS 0, RO/COR RX FIFO Under Flow Status:

0 = Normal.

1 = Underflow detected.

1:0 ELAST_BUF[1:0] 01, RW Receive Elasticity Buffer:

This field controls the Receive Elasticity Buffer which allows for frequency variation

tolerance between the 50 MHz RMII clock and the recovered data. See Section 6.2

for more information on Elasticity Buffer settings in RMII mode. See Section 6.4 for

more information on Elasticity Buffer settings in SCMII mode.

10.2.5 LED Direct Control Register (LEDCR)

This register provides the ability to directly control any or all LED outputs. It does not provide read access

to LEDs. In addition, it provides control for the Activity source and blinking LED frequency.

Table 10-20. LED Direct Control Register (LEDCR), address 18h

Bit Bit Name Default Description

15:9 RESERVED 0, RO RESERVED: Writes ignored, read as 0.

8 LEDACT_RX 0, RW 1 = Activity is only indicated for Receive traffic

0 = Activity is indicated for Transmit or Receive traffic

7:6 BLINK_FREQ 00, RW LED Blink Frequency:

These bits control the blink frequency of the LED_LINK output when blinking on

activity is enabled.

0 = 6Hz

1 = 12Hz

2 = 24Hz

3 = 48Hz

5 DRV_SPDLED 0, RW 1 = Drive value of SPDLED bit onto LED_SPEED output

0 = Normal operation

4 DRV_LNKLED 0, RW 1 = Drive value of LNKLED bit onto LED_LINK output

0 = Normal operation

3 DRV_ACTLED 0, RW 1 = Drive value of ACTLED bit onto LED_ACT/LED_COL output

0 = Normal operation

2 SPDLED 0, RW Value to force on LED_SPEED output

1 LNKLED 0, RW Value to force on LED_LINK output

0 ACTLED 0, RW Value to force on LED_ACT/LED_COL output

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