Datasheet

DP83849IF

SNOSAX8D –JUNE 2009–REVISED APRIL 2013

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10.1.13 Page Select Register (PAGESEL)

This register is used to enable access to the Link Diagnostics Registers.

Table 10-15. Page Select Register (PAGESEL), address 13h

Bit Bit Name Default Description

15:2 RESERVED 0, RO RESERVED: Writes ignored, read as 0

1:0 PAGE_SEL 0, RW Page_Sel Bit:

Selects between paged registers for address 14h to 1Fh.

0 = Extended Registers Page 0

1 = RESERVED

2 = Link Diagnostics Registers Page 2

10.2 EXTENDED REGISTERS - PAGE 0

10.2.1 False Carrier Sense Counter Register (FCSCR)

This counter provides information required to implement the “False Carriers” attribute within the MAU

managed object class of Clause 30 of the IEEE 802.3u specification.

Table 10-16. False Carrier Sense Counter Register (FCSCR), address 14h

Bit Bit Name Default Description

15:8 RESERVED 0, RO RESERVED: Writes ignored, read as 0

7:0 FCSCNT[7:0] 0, RO/COR False Carrier Event Counter:

This 8-bit counter increments on every false carrier event. This counter sticks when

it reaches its max count (FFh).

10.2.2 Receiver Error Counter Register (RECR)

This counter provides information required to implement the “Symbol Error During Carrier” attribute within

the PHY managed object class of Clause 30 of the IEEE 802.3u specification.

Table 10-17. Receiver Error Counter Register (RECR), address 15h

Bit Bit Name Default Description

15:8 RESERVED 0, RO RESERVED: Writes ignored, read as 0.

7:0 RXERCNT[7:0] 0, RO/COR RX_ER Counter:

When a valid carrier is present and there is at least one occurrence of an invalid

data symbol, this 8-bit counter increments for each receive error detected. This

event can increment only once per valid carrier event. If a collision is present, the

attribute will not increment. The counter sticks when it reaches its max count.

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