Datasheet

DP83849IF
SNOSAX8D –JUNE 2009–REVISED APRIL 2013 www.ti.com
Table 10-12. PHY Status Register (PHYSTS), address 10h (continued)
Bit Bit Name Default Description
5 JABBER DETECT 0, RO Jabber Detect: This bit only has meaning in 10 Mb/s mode.
This bit is a duplicate of the Jabber Detect bit in the BMSR register, except that
it is not cleared upon a read of the PHYSTS register.
1 = Jabber condition detected.
0 = No Jabber.
4 AUTO-NEG COMPLETE 0, RO Auto-Negotiation Complete:
1 = Auto-Negotiation complete.
0 = Auto-Negotiation not complete.
3 LOOPBACK STATUS 0, RO Loopback:
1 = Loopback enabled.
0 = Normal operation.
2 DUPLEX STATUS 0, RO Duplex:
This bit indicates duplex status and is determined from Auto-Negotiation or
Forced Modes
(1)
.
1 = Full duplex mode.
0 = Half duplex mode.
1 SPEED STATUS 0, RO Speed10:
This bit indicates the status of the speed and is determined from Auto-
Negotiation or Forced Modes
(1)
.
1 = 10 Mb/s mode.
0 = 100 Mb/s mode.
0 LINK STATUS 0, RO Link Status:
This bit is a duplicate of the Link Status bit in the BMSR register, except that it
will not be cleared upon a read of the PHYSTS register.
1 = Valid link established (for either 10 or 100 Mb/s operation).
0 = Link not established.
(1) This bit is only valid if Auto-Negotiation is enabled and complete and there is a valid link or if Auto-Negotiation is disabled and there is a
valid link.
10.1.11 MII Interrupt Control Register (MICR)
This register implements the MII Interrupt PHY Specific Control register. Sources for interrupt generation
include: Energy Detect State Change, Link State Change, Speed Status Change, Duplex Status Change,
Auto-Negotiation Complete or any of the counters becoming half-full. The individual interrupt events must
be enabled by setting bits in the MII Interrupt Status and Event Control Register (MISR).
Table 10-13. MII Interrupt Control Register (MICR), address 11h
Bit Bit Name Default Description
15:3 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
2 TINT 0, RW Test Interrupt:
Forces the PHY to generate an interrupt to facilitate interrupt testing. Interrupts will
continue to be generated as long as this bit remains set.
1 = Generate an interrupt.
0 = Do not generate interrupt.
1 INTEN 0, RW Interrupt Enable:
Enable interrupt dependent on the event enables in the MISR register.
1 = Enable event based interrupts.
0 = Disable event based interrupts.
0 INT_OE 0, RW Interrupt Output Enable:
Enable interrupt events to signal via the PWRDOWN_INT pin by configuring the
PWRDOWN_INT pin as an output.
1 = PWRDOWN_INT is an Interrupt Output.
0 = PWRDOWN_INT is a Power Down Input.
82 Register Block Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DP83849IF