Datasheet

DP83849IF
SNOSAX8D –JUNE 2009–REVISED APRIL 2013 www.ti.com
Table 10-2. Register Table (continued)
Register Name Addr Tag Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
LED Direct Control 18h LEDCR Reserved Reserved Reserved Reserved Reserved Reserved Reserved LEDACT_R BLINK_FR BLINK_FR DRV_SPDLE DRV_LNKL DRV_ACTLE SPDLED LNKLED ACTLED
Register X EQ EQ D ED D
PHY Control 19h PHYCR MDIX_EN FORCE_M PAUSE_R PAUSE_TX BIST_FE PSR_15 BIST_ BIST_STA BP_STRET LED_ LED_ PHY PHY PHY PHY PHY
Register DIX X RT CH
STATUS CNFG[1] CNFG[0] ADDR ADDR ADDR ADDR ADDR
10Base-T 1Ah 10BT_SER Reserved Reserved Reserved Reserved SQUELCH SQUELCH SQUELCH LOOPBAC LP_DIS FORCE_ Reserved POLARITY Reserved Reserved HEARTBEAT JABBER_D
Status/Control IAL K_10_DIS _DIS IS
LINK_10
Register
CD Test Control 1Bh CDCTRL1 BIST_ERR BIST_ERR BIST_ERR BIST_ERR BIST_ERR BIST_ERR BIST_ERR BIST_ERR Reserved Reserved BIST_CONT_ CDPattEN_ Reserved 10Meg_Pat CDPattSel CDPattSel
and BIST OR_COUN OR_COUN OR_COUN OR_COUN OR_COUN OR_COUN OR_COUN OR_COUN MODE 10 t_Gap
Extensions T T T T T T T T
Register
Phy Control 1Ch PHYCR2 Reserved Reserved Reserved Reserved Reserved Reserved SOFT_RE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Register 2 SET
Energy Detect 1Dh EDCR ED_EN ED_AUTO ED_AUTO ED_MAN ED_BURS ED_PWR_ ED_ERR_ ED_DATA_ ED_ERR_ ED_ERR_ ED_ERR_CO ED_ERR_ ED_DATA_C ED_DATA_ ED_DATA_C ED_DATA_
Control Register _UP _DOWN T_DIS STATE MET MET COUNT COUNT UNT COUNT OUNT COUNT OUNT COUNT
RESERVED 1Eh-1Fh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
RESERVED REGISTERS
RESERVED 14h-1Fh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
LINK DIAGNOSTICS REGISTERS - PAGE 2
100Mb Length 14h LEN100_D Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CABLE_LE CABLE_LE CABLE_LEN CABLE_LE CABLE_LEN CABLE_LE CABLE_LEN CABLE_LE
Detect Register ET N N N N N
100Mb Frequency 15h FREQ100 SAMPLE_F Reserved Reserved Reserved Reserved Reserved Reserved SEL_FC FREQ_OF FREQ_OF FREQ_OFFS FREQ_OF FREQ_OFFS FREQ_OF FREQ_OFFS FREQ_OF
Offset Indication REQ FSET FSET ET FSET ET FSET ET FSET
Register
TDR Control 16h TDR_CTRL TDR_ENA TDR_100M TX_CHAN RX_CHAN SEND_TD TDR_WIDT TDR_WIDT TDR_WIDT TDR_MIN_ Reserved RX_THRESH RX_THRE RX_THRESH RX_THRE RX_THRESH RX_THRE
Register BLE b NEL NEL R H H H MODE OLD SHOLD OLD SHOLD OLD SHOLD
TDR Window 17h TDR_WIN TDR_STA TDR_STA TDR_STA TDR_STA TDR_STA TDR_STA TDR_STA TDR_STA TDR_STO TDR_STO TDR_STOP TDR_STO TDR_STOP TDR_STO TDR_STOP TDR_STO
Register RT RT RT RT RT RT RT RT P P P P P
TDR Peak 18h TDR_PEA Reserved Reserved TDR_PEA TDR_PEA TDR_PEA TDR_PEA TDR_PEA TDR_PEA TDR_PEA TDR_PEA TDR_PEAK_ TDR_PEA TDR_PEAK_ TDR_PEA TDR_PEAK_ TDR_PEA
Register K K K K K K K K_TIME K_TIME TIME K_TIME TIME K_TIME TIME K_TIME
TDR Threshold 19h TDR_THR Reserved Reserved Reserved Reserved Reserved Reserved Reserved TDR_THR_ TDR- TDR- TDR- TDR- TDR- TDR- TDR- TDR-
Register MET THR_TIME THR_TIME THR_TIME THR_TIME THR_TIME THR_TIME THR_TIME THR_TIME
Variance Control 1Ah VAR_CTRL VAR_RDY Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved VAR_FREEZ VAR_TIME VAR_TIMER VAR_TIME
Register E R R
Variance Data 1Bh VAR_DAT VAR_DAT VAR_DAT VAR_DAT VAR_DAT VAR_DAT VAR_DAT VAR_DAT VAR_DAT VAR_DAT VAR_DAT VAR_DATA VAR_DAT VAR_DATA VAR_DAT VAR_DATA VAR_DAT
Register A A A A A A A A A A A A A A
RESERVED 1Ch Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Link Quality 1Dh LQMR LQM_ENA Reserved Reserved Reserved Reserved Reserved FC_HI_WA FC_LO_W FREQ_HI_ FREQ_LO_ DBLW_HI_W DBLW_LO DAGC_HI_W DAGC_LO C1_HI_WAR C1_LO_W
Monitor Register BLE RN ARN WARN WARN ARN _WARN ARN _WARN N ARN
Link Quality Data 1Eh LQDR Reserved Reserved SAMPLE_ WRITE_LQ LQ_PARA LQ_PARA LQ_PARA LQ_THR_S LQ_THR_D LQ_THR_D LQ_THR_DA LQ_THR_D LQ_THR_DA LQ_THR_D LQ_THR_DA LQ_THR_D
Register PARAM _THR M_SEL M_SEL M_SEL EL ATA ATA TA ATA TA ATA TA ATA
RESERVED 1Fh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
72 Register Block Copyright © 2009–2013, Texas Instruments Incorporated
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