Datasheet

Pin 31 (PFBOUT)

Pin 7 (PFBIN1)

Pin 28 (PFBIN2)

Pin34 (PFBIN3)

Pin 54 (PFBIN4)

0.1 PF

10 PF

0.1 PF

DP83849IF

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SNOSAX8D –JUNE 2009–REVISED APRIL 2013

8.5 POWER FEEDBACK CIRCUIT

To ensure correct operation for the DP83849IF, parallel caps with values of 10 µF and 0.1 µF should be

placed close to pin 31 (PFBOUT) of the device. Pin 7 (PFBIN1), pin 28 (PFBIN2), pin 34 (PFBIN3) and

pin 54 (PFBIN4) must be connected to pin 31 (PFBOUT), each pin requires a small capacitor (.1 µF). See

Figure 8-4 below for proper connections.

Figure 8-4. Power Feedback Connection

8.6 POWER DOWN/INTERRUPT

The Power Down and Interrupt functions are multiplexed on pin 18 and pin 44 of the device. By default,

this pin functions as a power down input and the interrupt function is disabled. Setting bit 0 (INT_OE) of

MICR (11h) will configure the pin as an active low interrupt output. Ports A and B can be powered down

individually, using the separate PWRDOWN_INT_A and PWRDOWN_INT_B pins.

8.6.1 Power Down Control Mode

The PWRDOWN_INT pins can be asserted low to put the device in a Power Down mode. This is

equivalent to setting bit 11 (Power Down) in the Basic Mode Control Register, BMCR (00h). An external

control signal can be used to drive the pin low, overcoming the weak internal pull-up resistor. Alternatively,

the device can be configured to initialize into a Power Down state by use of an external pull-down resistor

on the PWRDOWN_INT pin. Since the device will still respond to management register accesses, setting

the INT_OE bit in the MICR register will disable the PWRDOWN_INT input, allowing the device to exit the

Power Down state.

8.6.2 Interrupt Mechanisms

Since each port has a separate interrupt pin, the interrupts can be connected individually or may be

combined in a wired-OR fashion. If the interrupts share a single connection, each port status should be

checked following an interrupt.

The interrupt function is controlled via register access. All interrupt sources are disabled by default. Setting

bit 1 (INTEN) of MICR (11h) will enable interrupts to be output, dependent on the interrupt mask set in the

lower byte of the MISR (12h). The PWRDOWN_INT pin is asynchronously asserted low when an interrupt

condition occurs. The source of the interrupt can be determined by reading the upper byte of the MISR.

One or more bits in the MISR will be set, denoting all currently pending interrupts. Reading of the MISR

clears ALL pending interrupts.

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