Datasheet

4B/5B DECODER
DESCRAMBLER
RX_CLK RXD[3:0] / RX_ER
CODE GROUP
ALIGNMENT
SERIAL TO
PARALLEL
RX_DV/CRS
RD +/-
DIGITAL
SIGNAL
PROCESSOR
ANALOG
FRONT
END
SIGNAL
DETECT
MLT-3 TO BINARY
DECODER
NRZI TO NRZ
DECODER
LINK
INTEGRITY
MONITOR
RX_DATA VALID
SSD DETECT
DP83849IF
www.ti.com SNOSAX8D –JUNE 2009–REVISED APRIL 2013
7.2.1 Analog Front End
In addition to the Digital Equalization and Gain Control, the DP83849IF includes Analog Equalization and
Gain Control in the Analog Front End. The Analog Equalization reduces the amount of Digital Equalization
required in the DSP.
7.2.2 Digital Signal Processor
The Digital Signal Processor includes Adaptive Equalization with Gain Control and Base Line Wander
Compensation.
Figure 7-2. 100BASE-TX Receive Block Diagram
Copyright © 2009–2013, Texas Instruments Incorporated Architecture 51
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