Datasheet

DP83849IF
www.ti.com SNOSAX8D –JUNE 2009–REVISED APRIL 2013
The DP83849IF requires a single initialization sequence of 32 bits of preamble following
hardware/software reset. This requirement is generally met by the mandatory pull-up resistor on MDIO in
conjunction with a continuous MDC, or the management access made to determine whether Preamble
Suppression is supported.
While the DP83849IF requires an initial preamble sequence of 32 bits for management initialization, it
does not require a full 32-bit sequence between each subsequent transaction. A minimum of one idle bit
between management transactions is required as specified in the IEEE 802.3u specification.
6.6.4 Simultaneous Register Write
The DP83849IF incorporates a mode which allows simultaneous write access to both Port A and B
register blocks at the same time. This mode is selected by setting bit 15 of RMII and Bypass Register
(RBR, address 17h) in Port A.
As long as this bit remains set, subsequent writes to Port A will write to registers in both ports.
Register reads are unaffected. Each port must still be read individually.
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