Datasheet

z
z
z
z
Register DataTA IdleRegister Address
(00h = BCMR)
PHY Address
(PHY AD = 0Ch)
Opcode
(Write)
StartIdle
MDC
MDIO
(STA)
0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0 01
z
z
z
z
z
z
Register DataTA IdleRegister Address
(00h = BCMR)
PHY Address
(PHY AD = 0Ch)
Opcode
(Read)
StartIdle
MDC
MDIO
MDIO
(STA)
(PHY)
z
0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0
DP83849IF
SNOSAX8D –JUNE 2009–REVISED APRIL 2013 www.ti.com
In addition, the MDIO pin requires a pull-up resistor (1.5 kΩ) which, during IDLE and turnaround, will pull
MDIO high. In order to initialize the MDIO interface, the station management entity sends a sequence of
32 contiguous logic ones on MDIO to provide the DP83849IF with a sequence that can be used to
establish synchronization. This preamble may be generated either by driving MDIO high for 32
consecutive MDC clock cycles, or by simply allowing the MDIO pull-up resistor to pull the MDIO pin high
during which time 32 MDC clock cycles are provided. In addition 32 MDC clock cycles should be used to
re-sync the device if an invalid start, opcode, or turnaround bit is detected.
The DP83849IF waits until it has received this preamble sequence before responding to any other
transaction. Once the DP83849IF serial management port has been initialized no further preamble
sequencing is required until after a power-on/reset, invalid Start, invalid Opcode, or invalid turnaround bit
has occurred.
The Start code is indicated by a <01> pattern. This assures the MDIO line transitions from the default idle
line state.
Turnaround is defined as an idle bit time inserted between the Register Address field and the Data field.
To avoid contention during a read transaction, no device shall actively drive the MDIO signal during the
first bit of Turnaround. The addressed DP83849IF drives the MDIO with a zero for the second bit of
turnaround and follows this with the required data. Figure 6-2 shows the timing relationship between MDC
and the MDIO as driven/received by the Station (STA) and the DP83849IF (PHY) for a typical register
read access.
For write transactions, the station management entity writes data to the addressed DP83849IF thus
eliminating the requirement for MDIO Turnaround. The Turnaround time is filled by the management entity
by inserting <10>. Figure 6-3 shows the timing relationship for a typical MII register write access.
Figure 6-2. Typical MDC/MDIO Read Operation
Figure 6-3. Typical MDC/MDIO Write Operation
6.6.3 Serial Management Preamble Suppression
The DP83849IF supports a Preamble Suppression mode as indicated by a one in bit 6 of the Basic Mode
Status Register (BMSR, address 01h.) If the station management entity (i.e. MAC or other management
controller) determines that all PHYs in the system support Preamble Suppression by returning a one in
this bit, then the station management entity need not generate preamble for each management
transaction.
46 MAC Interface Copyright © 2009–2013, Texas Instruments Incorporated
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