Datasheet

DP83849IF
www.ti.com SNOSAX8D –JUNE 2009–REVISED APRIL 2013
The elasticity buffer will force Frame Check Sequence errors for packets which overrun or underrun the
FIFO. Underrun and Overrun conditions can be reported in the RMII and Bypass Register (RBR). The
following table indicates how to program the elasticity buffer fifo (in 4-bit increments) based on expected
max packet size and clock accuracy. It assumes both clocks (RMII Reference clock and far-end
Transmitter clock) have the same accuracy.
Packet lengths can be scaled linearly based on accuracy (+/- 25ppm would allows packets twice as large).
If the threshold setting must support both 10Mb and 100Mb operation, the setting should be made to
support both speeds.
Table 6-1. Supported Packet Sizes at +/-50ppm Frequency Accuracy
Latency Tolerance Recommended Packet Size at +/- 50ppm
Start Threshold RBR[1:0]
100Mb 10Mb 100Mb 10Mb
01 (default) 2 bits 8 bits 2,400 bytes 9,600 bytes
10 6 bits 4 bits 7,200 bytes 4,800 bytes
11 10 bits 8 bits 12,000 bytes 9,600 bytes
00 14 bits 12 bits 16,800 bytes 14,400 bytes
6.3 10 Mb SERIAL NETWORK INTERFACE (SNI)
The DP83849IF incorporates a 10 Mb Serial Network Interface (SNI) which allows a simple serial data
interface for 10 Mb only devices. This is also referred to as a 7-wire interface. While there is no defined
standard for this interface, it is based on early 10 Mb physical layer devices. Data is clocked serially at 10
MHz using separate transmit and receive paths. The following pins are used in SNI mode:
• TX_CLK
• TX_EN
• TXD[0]
• RX_CLK
• RXD[0]
• CRS
• COL
6.4 SINGLE CLOCK MII MODE
Single Clock MII (SCMII) Mode allows MII operation using a single 25 MHz reference clock. Normal MII
Mode requires three clocks, a reference clock for physical layer functions, a Transmit MII clock, and a
Receive MII clock. Similar to RMII mode, Single Clock MII mode requires only the reference clock. In
addition to reducing the number of pins required, this mode allows the attached MAC device to use only
the reference clock domain. Since the DP83849IF has two ports, this actually reduces the number of
clocks from 6 to 1. A/C Timing requirements for SCMII operation are similar to the RMII timing
requirements.
For 10Mb operation, as in RMII mode, data is sampled and driven every 10 clocks since the reference
clock is at 10x the data rate.
Separate control bits allow enabling the Transmit and Receive Single Clock modes separately, allowing
just transmit or receive to operate in this mode. Control of Single Clock MII mode is through the RBR
register.
Single Clock MII mode incorporates the use of the RMII elasticity buffer, which is required to tolerate
potential frequency differences between the 25 MHz reference clock and the recovered receive clock.
Settings for the Elasticity Buffer for SCMII mode are detailed in the following table.
Copyright © 2009–2013, Texas Instruments Incorporated MAC Interface 41
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